IBM Intel Xeon E5606 81Y9324 User Manual

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PROCHOT#

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PROCHOT# will go active when the processor temperature monitoring sensor 

detects that the processor has reached its maximum safe operating 

temperature. This indicates that the processor Thermal Control Circuit has 

been activated, if enabled. This signal can also be driven to the processor to 

activate the Thermal Control Circuit. 
If PROCHOT# is asserted at the deassertion of RESET# on DP enabled 

products, the processor will tri-state its outputs. This signal does not have on-

die termination and must be terminated on the system board.

PSI#

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Processor Power Status Indicator signal. This signal is asserted when maximum 

possible processor core current consumption is less than 20A, Assertion of this 

signal is an indication that the VR controller does not currently need to be able 

to provide ICC above 20A, and the VR controller can use this information to 

move to more efficient operation point. 

RESET#

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Asserting the RESET# signal resets the processor to a known state and 

invalidates its internal caches without writing back any of their contents. Note 

some PLL, Intel QuickPath Interconnect and error states are not affected by 

reset and only VCCPWRGOOD forces them to a known state. For a power-on 

Reset, RESET# must stay active for at least one millisecond after VCC and 

BCLK have reached their proper specifications. RESET# must not be kept 

asserted for more than 10 ms while VCCPWRGOOD is asserted. RESET# must 

be held deasserted for at least one millisecond before it is asserted again. 

RESET# must be held asserted before VCCPWRGOOD is asserted. This signal 

does not have on-die termination and must be terminated on the system 

board. RESET# is a common clock signal.

SKTOCC#

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Socket occupied. The platform designer can use this signal to enable power 

supplies when there is a CPU occupying the socket. 
Requires external pull-up. 

TAPPWRGOOD

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Processor output signal, which when deasserted indicates the processor is in a 

low power state and TAP functionality is unavailable.

TCK

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TCK (Test Clock) provides the clock input for the processor Test Bus (also 

known as the Test Access Port).

TDI

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TDI (Test Data In) transfers serial test data into the processor. TDI provides the 

serial input needed for JTAG specification support.

TDO

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TDO (Test Data Out) transfers serial test data out of the processor. TDO 

provides the serial output needed for JTAG specification support.

THERMTRIP#

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Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction 

temperature has reached a level beyond which permanent silicon damage may 

occur. Measurement of the temperature is accomplished through an internal 

thermal sensor. Once activated, the processor will stop all execution and shut 

down all PLLs. To further protect the processor, its core voltage (V

CC

), V

TTA

 V

TTD

 

and V

DDQ

 must be removed following the assertion of THERMTRIP#. See 

 and 

 for the appropriate power down sequence and 

timing requirements. Once activated, THERMTRIP# remains latched until 

RESET# is asserted. While the assertion of the RESET# signal may de-assert 

THERMTRIP#, if the processor's junction temperature remains at or above the 

trip level, THERMTRIP# will again be asserted after RESET# is de-asserted.

TMS

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TMS (Test Mode Select) is a JTAG specification support signal used by debug 

tools.

TRST#

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TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be 

driven low during power on Reset.

VCC_SENSE
VSS_SENSE

O
O

VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to 

the processor core voltage and ground. They can used to sense or measure 

power near the silicon with little noise.

V

CC

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Power for processor core.