IBM Intel Xeon E5606 81Y9324 User Manual
Product codes
81Y9324
Thermal Specifications
134
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
With a properly designed and characterized thermal solution, it is anticipated that
PROCHOT# will only be asserted for very short periods of time when running the most
power intensive applications. An under-designed thermal solution that is not able to
prevent excessive assertion of PROCHOT# in the anticipated ambient environment may
cause a noticeable performance loss.
PROCHOT# will only be asserted for very short periods of time when running the most
power intensive applications. An under-designed thermal solution that is not able to
prevent excessive assertion of PROCHOT# in the anticipated ambient environment may
cause a noticeable performance loss.
7.2.5
THERMTRIP# Signal
Regardless of whether Adaptive Thermal Monitor is enabled, in the event of a
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached an elevated temperature (refer to the THERMTRIP# definition in
catastrophic cooling failure, the processor will automatically shut down when the silicon
has reached an elevated temperature (refer to the THERMTRIP# definition in
). At this point, the THERMTRIP# signal will go active and stay active.
THERMTRIP# activation is independent of processor activity and does not generate any
Intel
Intel
QuickPath Interconnect transactions. If THERMTRIP# is asserted, processor V
CC
and V
TT
must be removed within the timeframe defined in
. The temperature
at which THERMTRIP# asserts is not user configurable and is not software visible.
7.3
Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
The PECI bus offers:
• A wide speed range from 2 kbps to 2 Mbps
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
• CRC check byte used to efficiently and atomically confirm accurate data delivery
• Synchronization at the beginning of every message minimizes device timing
accuracy requirements
Intel recommends PECI host device speeds of 1.2 Mbps or lower for platforms using the
Intel Xeon processor 5600 series. PECI host devices operating at speeds greater than
1.2 Mbps may get a CPU “Timeout” error response to the PCI-ConfigRd() and
PCICconfigWr() PECI commands. This is expected to happen only during the deepest
idle states on Intel Xeon processor 5600 series. If higher bit rates are required,
platforms must be tolerant of “Timeout” completion codes during the deepest processor
package C-states. Please note that processors always request a 2 Mbps bit rate, and
Intel Xeon processor 5600 series. PECI host devices operating at speeds greater than
1.2 Mbps may get a CPU “Timeout” error response to the PCI-ConfigRd() and
PCICconfigWr() PECI commands. This is expected to happen only during the deepest
idle states on Intel Xeon processor 5600 series. If higher bit rates are required,
platforms must be tolerant of “Timeout” completion codes during the deepest processor
package C-states. Please note that processors always request a 2 Mbps bit rate, and