IBM Intel Xeon E5606 81Y9324 User Manual
Product codes
81Y9324
Electrical Specifications
28
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
2.2
Signal Group Summary
Signals are aligned in
by buffer type and characteristics. “Buffer Type”
denotes the applicable signaling technology and specifications.
Table 2-5.
Signal Groups (Sheet 1 of 2)
Signal Group
Buffer Type
Signals
1
Intel®
QuickPath Interconnect Signals
Differential
Intel®
QuickPath Interconnect Input
QPI[0/1]_DRX_D[N/P][19:0],
QPI[0/1]_CLKRX_DP, QPI[0/1]_CLKRX_DN
Differential
Intel®
QuickPath Interconnect Output
QPI[0/1]_DTX_D[N/P][19:0],
QPI[0/1]_CLKTX_DP, QPI[0/1]_CLKTX_DN
Single ended
Analog Input
QPI[0/1]_COMP
DDR3 Reference Clocks
2
Differential
Output
DDR{0/1/2}_CLK_[P/N][3:0]
DDR3 Command Signals
2
Single ended
CMOS Output
DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#,
DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0],
DDR{0/1/2}_BA[2:0], DDR{0/1/2}_MA_PAR
Asynchronous Output
DDR{0/1/2}_RESET#
DDR3 Control Signals
2
Single ended
CMOS Output
DDR{0/1/2}_CS#[7:0], DDR{0/1/2}_ODT[5:0],
DDR{0/1/2}_CKE[3:0]
Single ended
Analog Input
DDR_VREF, DDR_COMP[2:0]
DDR3 Data Signals
2
Single ended
CMOS Input/Output
DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_ECC[7:0]
Differential
CMOS Input/Output
DDR{0/1/2}_DQS_[N/P][17:0]
Single ended
Asynchronous Input
DDR{0/1/2}_PAR_ERR#[2:0],
DDR_THERM#, DDR_THERM2#
Platform Environmental Control Interface (PECI)
Single ended
Asynchronous Input/Output
PECI
Processor Sideband Signals
Single ended
GTL Input/Output
BPM#[7:0], CAT_ERR#
Single ended
Asynchronous Input
PECI_ID#
Single ended
Asynchronous GTL Output
PRDY#, THERMTRIP#
Single ended
Asynchronous GTL Input
PREQ#
Single ended
Asynchronous GTL Input/Output
PROCHOT#
Single ended
Asynchronous CMOS Output
PSI#, TAPPWRGOOD
Single ended
CMOS Output
VID[7:6],
VID[5:3]/CSC[2:0],
VID[2:0]/MSID[2:0],
VTT_VID[4:2]
VID[5:3]/CSC[2:0],
VID[2:0]/MSID[2:0],
VTT_VID[4:2]
PWRGOOD Signal
Single ended
Asynchronous Input
VCCPWRGOOD, VDDPWRGOOD, VTTPWRGOOD
Reset Signal
Single ended
Reset Input
RESET#