IBM Intel Xeon E5606 81Y9324 User Manual
Product codes
81Y9324
Electrical Specifications
50
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
SSC is Spread Spectrum Clocking. The processor core clock frequency is derived from BCLK. The system
reference clock to processor core clock ratio is determined during initialization as described in
3.
Rise and fall time slopes (V/ns) are measured between +150 mV and -150 mV of the differential output of
reference clock.
4.
Phase drift between reference clocks at two connected ports.
ER
BCLK-diffRise
, ER
BCLK-diffFall
1.0
4.0
V/ns
3
T
BCLK-Dutycycle
40
50
60
%
T
BCLK-diff-jit
500
ps
4
Table 2-22. System Reference Clock AC Specifications (Sheet 2 of 2)
Parameter
Min
Nom
Max
Unit
Figure
Notes
1
Table 2-23. DDR3/DDR3L Electrical Characteristics and AC Specifications at 800 MT/s
(Sheet 1 of 2)
Symbol
Parameter
Channel 0
Channel 1
Channel 2
Unit
Figure
Note
Max
Min
Latency Timings
tCL – tRCD – tRP
CAS Latency – RAS to CAS Delay –
Pre-charge Command Period
6 – 6 – 6
t
CK
Electrical Characteristics
T
SLR_D
DQ[63:0], DQS_N[17:0],
DQS_P[17:0], ECC[7:0]
Input Slew Rate
Input Slew Rate
4.0
1.0
V/ns
2
Clock Timings
T
CK
CLK Period
3
2.50
ns
T
CH
CLK High Time
1.50
1.25
ns
T
CL
CLK Low Time
1.50
1.25
ns
T
SKEW
Skew Between Any System
Memory Differential Clock Pair
(CLK_P/CLK_N)
+155
ps
Command Signal Timings
T
CMD_CO
RAS#, CAS#, WE#, MA[15:0],
BA[2:0] Edge placement accuracy
+375
-375
ps
3,4,6
Control Signal Timings
T
CTRL_CS
CS#[7:0], CKE[3:0], ODT[3:0]
Edge placement accuracy
+375
-375
ps
3,6
Data and Strobe Signal Timings
T
DVA
+ T
DVB
DQ[63:0] Valid before and after
DQS[17:0] Rising or Falling Edge
0.67 * UI
UI
7
T
SU
+ T
HD
DQ Input Setup plus Hold Time to
DQS Rising or Falling Edge
0.25 * UI
ns
1,2,7
T
DQS_CO
DQS Edge Placement Accuracy to
CK Rising Edge BEFORE write
leveling
+375
-375
ns
3,6,7