IBM Intel Xeon E5606 81Y9324 User Manual

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6.

The system memory clock outputs are differential (CLK and CLK#), the CLK rising edge is referenced at the 

crossing point where CLK is rising and CLK# is falling.

7.

The system memory strobe outputs are differential (DQS and DQS#), the DQS rising edge is referenced at 

the crossing point where DQS is rising and DQS# is falling, and the DQS falling edge is referenced at the 

crossing point where DQS is falling and DQS# is rising.

8.

This values specifies the parameter after write leveling, representing the residual error in the controller 

afrter training, and does not include any effects from the DRAM itself.

tCL – tRCD – tRP

CAS Latency – RAS to CAS Delay – 

Pre-charge Command Period

8 - 8 - 8
9 - 9 - 9

tCK

Electrical Characteristics

T

SLR_D

DQ[63:0], DQS_N[17:0], 

DQS_P[17:0], ECC[7:0], MA[15:0] 

Input Slew Rate

4.0

1.0

V/ns

2

T

CK

CLK Period

<1.875

1.50

ns

T

CH

CLK High Time

0.94

0.75

ns

T

CL

CLK Low Time

0.94

0.75

ns

T

SKEW

Skew Between Any System 

Memory Differential Clock Pair 

(CLK_P/CLK_N)

+155

ps

T

CMD_CO 

RAS#, CAS#, WE#, MA[15:0], 

BA[2:0] Edge placement accuracy

+250

-250

ps

3,4,6

T

CTRL_CS

CS#[7:0], CKE[3:0], ODT[3:0] 

Edge placement accuracy

+250

-250

ps

3,6

T

DVA 

+ T

DVB

DQ[63:0] Valid before and after 

DQS[17:0] Rising or Falling Edge

0.67 * UI

UI

7

T

SU

 + T

HD

DQ Input Setup plus Hold Time to 

DQS Rising or Falling Edge

0.25 * UI

ns

1,2,7

T

DQS_CO

DQS Edge Placement Accuracy to 

CK Rising Edge BEFORE write 

leveling

+250

-250

ns

3,6,7

T

DQS_CO

DQS Edge Placement Accuracy to 

CK Rising Edge AFTER write 

leveling

+165

-165

ns

3,6,7,8