IBM Intel Xeon E5606 49Y3776 User Manual
Product codes
49Y3776
Electrical Specifications
18
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
The PECI interface operates at a nominal voltage set by V
TTD
. The set of DC electrical
is used with devices normally operating from a V
TTD
interface supply.
2.1.3.1
Input Device Hysteresis
The PECI client and host input buffers must use a Schmitt-triggered input design for
improved noise immunity. Please refer to
improved noise immunity. Please refer to
.
2.1.4
Processor Sideband Signals
Intel Xeon processor 5600 series include sideband signals that provide a variety of
functions. Details can be found in
functions. Details can be found in
All Asynchronous Processor Sideband signals are required to be asserted/deasserted
for at least eight BCLKs in order for the processor to recognize the proper signal state.
See
for at least eight BCLKs in order for the processor to recognize the proper signal state.
See
and
for DC and AC specifications, respectively. Refer to
for applicable signal integrity specifications.
2.1.5
System Reference Clock
The processor core, processor uncore, Intel QuickPath Interconnect link, and DDR3
memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.
There is no direct link between core frequency and Intel QuickPath Interconnect link
frequency (e.g., no core frequency to Intel QuickPath Interconnect multiplier). The
processor maximum core frequency, Intel QuickPath Interconnect link frequency and
DDR memory frequency are set during manufacturing. It is possible to override the
processor core frequency setting using software. This permits operation at lower core
frequencies than the factory set maximum core frequency.
memory interface frequencies are generated from BCLK_DP and BCLK_DN signals.
There is no direct link between core frequency and Intel QuickPath Interconnect link
frequency (e.g., no core frequency to Intel QuickPath Interconnect multiplier). The
processor maximum core frequency, Intel QuickPath Interconnect link frequency and
DDR memory frequency are set during manufacturing. It is possible to override the
processor core frequency setting using software. This permits operation at lower core
frequencies than the factory set maximum core frequency.
The processor core frequency is configured during reset by using values stored within
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits
[15:0].
the device during manufacturing. The stored value sets the lowest core multiplier at
which the particular processor can operate. If higher speeds are desired, the
appropriate ratio can be configured via the IA32_PERF_CTL MSR (MSR 199h); Bits
[15:0].
Figure 2-2. Input Device Hysteresis
Minimum V
P
Maximum V
P
Minimum V
N
Maximum V
N
PECI High Range
PECI Low Range
Valid Input
Signal Range
Signal Range
Minimum
Hysteresis
Hysteresis
V
TTD
PECI Ground