Intel Z670 AY80609007293AA Data Sheet
Product codes
AY80609007293AA
Signal Descriptions
14
Datasheet
Signal
Direction
Type
Description
CDVO_STALL#
I
AGTL+
Stall: Allows PCH to throttle the sending of display data.
CDVO_TXDPWR#
O
AGTL+
Line wakeup for output: When asserted, the PCH will
power-up its receivers on CDVO_TX[5:0] and
CDVO_TXSTB_ODD#.
CDVO_TXSTB_ODD#,
CDVO_TXSTB_EVEN#
O
AGTL+
Data strobe output: Strobes for CDVO_TX[5:0].
CDVO_VBLANK#
I
AGTL+
Vertical blank: Indication from PCH indicating the start of
the vertical blank period.
CDVO_GVREF
I
Analog
Strobe signals' reference voltage for CDVO: Externally
set by means of a passive voltage divider. Voltage should
be 2/3 V
CCP
when configured for GTL.
CDVO_CVREF
I
Analog
Non-Strobe Signals' Reference Voltage for CDVO:
Externally set by means of a passive voltage divider.
Voltage should be 2/3 V
CCP
when configured for GTL.
2.1.4
LVDS Display Port Interface
Table 2-6. LVDS Display Port Interface Signals
Signal
Direction
Type
Description
LA_DATAN[3:0]
O
LVDS
Differential Data Output (Negative)
LA_DATAP[3:0]
O
LVDS
Differential Data Output (Positive)
LA_CLKN
O
LVDS
Differential Clock Output (Negative)
LA_CLKP
O
LVDS
Differential Clock Output (Positive)
LA_IBG
I
Analog
External Voltage Ref BG: Connected to high-precision
resistor on motherboard to VSS.
LA_VBG
I
Analog
External Voltage Ref BG: Requires external 1.25 V ±2%
supply.