IBM Intel Xeon E5606 49Y3770 User Manual

Product codes

49Y3770

Intel

Xeon

Processor 5600 Series Datasheet Volume 1

165

Features

8.2.1

Thread and Core Power State Descriptions

Individual threads may request low power states as described below. Core power states
are automatically resolved by the processor as shown in

Table 8-2

Note:

If enabled, state will be C1E.

8.2.1.1

C0 State

This is the normal operating state in the processor.

8.2.1.2

C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon
occurrence of an interrupt or an access to the monitored address if the state was
entered via the MWAIT instruction. RESET# will cause the processor to initialize itself.

Figure 8-2. Power States

1. No transition to C0 is needed to service a snoop when in C1 or C1E.

2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was
entered via MWAIT).

C E

MWAIT C1,

HLT

MWAIT C1,

HLT

(C1E enabled)

MWAIT C3,

I/O C3

MWAIT C6,

I/O C6

Table 8-2.

Coordination of Thread Power States at the Core Level

Core State

Thread 1 State

Thread 0 State