IBM Intel Xeon E5606 49Y3770 User Manual

20

Processors also include various other signals including power/ground, sense points, and 
analog inputs. Details can be found in 

 outlines the required voltage supplies necessary to support Intel Xeon 

processor 5600 series.

1.

Refer to 

 for voltage and current specifications.

For clean on-chip power distribution, processors include lands for all required voltage 
supplies. These include:

• 210  each  V

CC

 (271 ea. V

SS

) lands must be supplied with the voltage determined by 

the VID[7:0] signals. 

 defines the voltage level associated with each core 

VID pattern. 

 represent V

CC 

static and transient limits.

• 3  each  V

CCPLL

 lands, connected to a 1.8 V supply, power the Phase Lock Loop (PLL) 

clock generation circuitry. An on-die PLL filter solution is implemented within the 
processor.

• 45 each V

DDQ

 (17 ea. V

SS

) lands, connected to a 1.50 / 1.35 V supply, provide 

power to the processor DDR3 interface. This supply also powers the DDR3 memory 
subsystem.

• 7  each  V

TTA

 (5 ea. V

SS

) and 26 ea. V

TTD

 (17 ea. V

SS

) lands must be supplied with 

the voltage determined by the VTT_VID[4:2] signals. Coupled with a 20 mV offset, 
this corresponds to a VTT_VID pattern of ‘010xxx10’. 

 specifies the 

voltage levels associated with each VTT

_

VID pattern. 

 and 

represent V

TT 

static and transient limits.

All V

CC

, V

CCPLL, 

V

DDQ, 

V

TTA

, and V

TTD

 lands must be connected to their respective 

processor power planes, while all V

SS

 lands must be connected to the system ground 

plane. 

Due to its large number of transistors and high internal clock speeds, the processor is 
capable of generating large current swings between low and full power states. This may 
cause voltages on power planes to sag below their minimum values if bulk decoupling is 
not adequate. Larger bulk storage (C

BULK

), such as electrolytic capacitors, supply 

V

CC

See 

; 

Each processor includes a dedicated VR11.1 regulator.

V

CCPLL

1.80 V

Each processor includes dedicated V

CCPLL 

and PLL circuits.

V

DDQ

1.50 V

1.35 V

Each processor and DDR3 / DDR3L stack shares a dedicated 
voltage regulator. It is expected that regulators will support 
both 1.50 and 1.35 V.

V

TTA

, V

TTD

See 

; 

Each processor includes a dedicated VR11.0 regulator.
V

TT 

= V

TTA

 + V

TTD

; P1V1_Vtt is VID[4:2] controlled, 

VID range is 1.025-1.2000V; 20 mV offset (see 

); 

V

TT

 represents a 

 voltage. V

TT_MIN

 and V

TT_MAX

 

loadlines represent a 31.5 mV offset from V

TT

 (typ).