IBM Intel Xeon E5606 49Y3770 User Manual
Product codes
49Y3770
Electrical Specifications
48
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
Used during initialization. It is the state of “OFF” condition for the transmitter. That is, when the output
driver is disconnected and only the minimum termination is connected. The link detection resistor is
assumed not connected when specifying this parameter.
2.
Used during initialization. It is the state of “OFF” condition for the receiver when only the minimum
termination is connected.
Notes:
1.
Refers to routing lengths of 10 - 15 inches (25.4 - 38.1 cm).
2.
Refers to routing lengths of 0 - 10 inches (0 - 25.4 cm).
Table 2-20. Parameter Values for Intel® QuickPath Interconnect Channels at 4.8 GT/s
Symbol
Parameter
Min
Max
Unit
Notes
V
Tx-diff-pp-pin
Transmitter differential swing
800
1400
mV
V
Tx-cm-dc-pin
Transmitter output DC common mode, defined as
average of V
D+
and V
D-
Use setup of
.
0.23
0.27
Fraction of
V
TX-diff-pp-pin
V
Tx-cm-ac-pin
Transmitter output AC common mode, defined as
((V
D+
+ V
D-
)/2 - V
Tx-cm-ac-pin
). Use setup of
for illustration of AC
common mode distribution and spec limits.
-0.0375
0.0375
Fraction of
V
TX-diff-pp-pin
TX
duty-pin
Average of UI-UI jitter, using setup of
This appears as bimodal peaks in UI-UI jitter
distribution
.
-0.078
0.078
UI
TX
jitUI-UI-1E-7pin
UI-UI jitter measured at Tx output pins with 1E-7
probability, using setup of
. Refer to
for illustration of UI-UI jitter distribution
and spec limits
-0.085
0.085
UI
TX
jitUI-UI-1E-9pin
UI-UI jitter measured at Tx output pins with 1E-9
probability, using setup of
. Refer to
for illustration of UI-UI jitter distribution
and spec limits
-0.09
0.09
UI
TX
clk-acc-jit-N_UI-1E-7
P-P accumulated jitter out of any Tx data or clock
over 0 <= n <= N UI where N=12, measured with
1E-7 probability. Refer to
for illustration
0
0.15
UI
TX
clk-acc-jit-N_UI-1E-9
P-P accumulated jitter out of any Tx data or clock
over 0 <= n <= N UI where N=12, measured with
1E-9 probability. Refer to
for illustration
0
0.17
UI
T
Tx-data-clk-skew-pin
Delay of any data lane relative to the clock lane, as
measured at Tx output
-0.4
0.4
UI
T
Rx-data-clk-skew-pin
Delay of any data lane relative to the clock lane, as
measured at Tx+ channel. This parameter is a
collective sum of effects of data clock mismatches in
Tx and on the medium connecting Tx and Rx.
0
2
UI
1
-1
1
2
V
Rx-cm-dc-pin
DC common mode ranges at the Rx input for any data
or clock channel, defined as average of V
D+
and V
D-
.
145
350
mV
V
Rx-cm-ac-pin
AC common mode ranges at the Rx input for any data
or clock channel, defined as((V
D+
+ V
D-
)/2 - V
RX-cm-
dc-pin
). Refer to
for illustration.
-50
50
mV
T
Rx-margin
Measured timing margin during receiver margining
with any receiver equalizer off or for Tx EQ only based
systems
0.1
UI