IBM Intel Xeon E5606 49Y3765 User Manual

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In the event that the processor is tri-stated using power-on-configuration controls, the 
PECI client will also be tri-stated.

The PECI client is available on all processors, and positive identification of the PECI 
revision number can be achieved by issuing the GetDIB() command. Please refer to 

 for details on GetDIB response formatting.

The PECI client assumes a default address of 0x30. If nothing special is done to the 
processor, all PECI clients will boot with this address. For DP enabled parts, a special 
PECI_ID# pin is available to strap each PECI socket to a different node ID. The package 
pin strap is evaluated at the assertion of VCCPWRGOOD (as depicted in 

Since PECI_ID# is active low, tying the pin to ground results in a client address of 
0x31, and tying it to V

TT

 results in a client address of 0x30.

The client address may not be changed after VCCPWRGOOD assertion, until the next 
power cycle on the processor. Removal of a processor from its socket or tri-stating a 
processor in a DP configuration will have no impact to the remaining non-tri-stated 
PECI client address.

The Intel Xeon processor 5600 series are fully functional under all core and package 
C-states. Support for package C-states is a function of processor SKU and platform 
capabilities. All package C-states (C1E, C3, C6) are documented here for completeness, 
but actual processor support for these C-states may vary.

Because the processor takes aggressive power savings actions under the deepest 
C-states, PECI requests may have an impact to platform power. The impact is 
documented below:

CSI training

idle

running

Reset uCode

Boot BIOS

In Reset

Data Not Rdy

Fully Operational

x

0b1 or 0b0