IBM Intel Xeon E5606 49Y3765 User Manual
Product codes
49Y3765
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
21
Electrical Specifications
current during longer lasting changes in current demand, for example coming out of an
idle condition. Similarly, they act as a storage well for current when entering an idle
condition from a running condition. Care must be taken in the baseboard design to
ensure that the voltages provided to the processor remain within the specifications
listed in
idle condition. Similarly, they act as a storage well for current when entering an idle
condition from a running condition. Care must be taken in the baseboard design to
ensure that the voltages provided to the processor remain within the specifications
listed in
. Failure to do so can result in timing violations or reduced lifetime of
the processor.
2.1.7.3
Processor V
CC
Voltage Identification (VID) Signals
The voltage set by the VID signals is the maximum reference voltage regulator (VR)
output to be delivered to the processor V
output to be delivered to the processor V
CC
lands. VID signals are CMOS push/pull
outputs. Please refer to
for the DC specifications for these signals.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core frequency may have different default VID settings.
devices at the same core frequency may have different default VID settings.
The processor uses eight voltage identification signals, VID[7:0], to support automatic
selection of power supply voltages.
selection of power supply voltages.
specifies the voltage level corresponding
to the state of VID[7:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers
to a low voltage level. If the processor socket is empty (SKTOCC# pulled high), or the
voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself.
to a low voltage level. If the processor socket is empty (SKTOCC# pulled high), or the
voltage regulation circuit cannot supply the voltage that is requested, the voltage
regulator must disable itself.
The processor provides the ability to operate while transitioning to an adjacent VID and
its associated processor core voltage (V
its associated processor core voltage (V
CC
). This is represented by a DC shift in the
loadline. It should be noted that a low-to-high or high-to-low voltage state change may
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the maximum specified VID are not permitted.
result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the maximum specified VID are not permitted.
includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained
as shown in
as shown in
.
The VRM or EVRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in
by the new VID. DC specifications for dynamic VID transitions are included in
, while AC specifications are included in
.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
the voltage regulator is stable.
Table 2-2.
Voltage Identification Definition (Sheet 1 of 6)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
V
CC_MAX
0
0
0
0
0
0
0
0
OFF
0
0
0
0
0
0
0
1
OFF
0
0
0
0
0
0
1
0
1.60000
0
0
0
0
0
0
1
1
1.59375
0
0
0
0
0
1
0
0
1.58750
0
0
0
0
0
1
0
1
1.58125
0
0
0
0
0
1
1
0
1.57500
0
0
0
0
0
1
1
1
1.56875
0
0
0
0
1
0
0
0
1.56250
0
0
0
0
1
0
0
1
1.55625
0
0
0
0
1
0
1
0
1.55000
0
0
0
0
1
0
1
1
1.54375