IBM Intel Xeon E5606 49Y3772 User Manual

111

BCLK_DN
BCLK_DP

I

Differential bus clock input to the processor.

BCLK_ITP_DN
BCLK_ITP_DP

O

Buffered differential bus clock pair to ITP.

BPM#[7:0]

I/O

BPM#[7:0] are breakpoint and performance monitor signals. They are outputs 

from the processor which indicate the status of breakpoints and programmable 

counters used for monitoring processor performance. BPM#[7:0] should be 

connected in a wired OR topology between all packages on a platform. 
BPM#[5] and BPM#[7] signals between the two processors must remain 

connected on production units.

CAT_ERR#

I/O

Indicates that the system has experienced a catastrophic error and cannot 

continue to operate. The processor will set this for non-recoverable machine 

check errors and other internal unrecoverable error. It is expected that every 

processor in the system will have this hooked up in a wired-OR configuration. 

Since this is an I/O pin, external agents are allowed to assert this pin which will 

cause the processor to take a machine check exception.
On Intel Xeon processor 5600 series, CAT_ERR# is used for signalling the 

following types of errors:

• Legacy MCERR’s, CAT_ERR# is pulsed for 16 BCLKs.
• Legacy IERR’s, CAT_ERR remains asserted until warm or cold reset.

COMP0

I

Impedance Compensation must be terminated on the system board using 

precision resistor.

QPI0_CLKRX_DN
QPI0_CLKRX_DP

I
I

Intel

 

QuickPath Interconnect received clock is the input clock that corresponds 

to Intel QuickPath Interconnect port0 received data.

QPI0_CLKTX_DN
QPI0_CLKTX_DP

O
O

Intel QuickPath Interconnect forwarded clock sent with Intel QuickPath 

Interconnect 0 port outbound data.

QPI0_COMP

I

Must be terminated on the system board using precision resistor.

QPI0_DRX_DN[19:0]
QPI0_DRX_DP[19:0]

I
I

QPI0_DRX_DN[19:0] and QPI0_DRX_DP[19:0] comprise the differential 

receive data for Intel QuickPath Interconnect port0. The inbound 20 lanes are 

connected to another component’s outbound lanes.

QPI0_DTX_DN[19:0]
QPI0_DTX_DP[19:0]

O
O

QPI0_DTX_DN[19:0] and QPI0_DTX_DP[19:0] comprise the differential 

transmit data for Intel QuickPath Interconnect port0. The outbound 20 lanes 

are connected to another component’s inbound lanes.

QPI1_CLKRX_DN
QPI1_CLKRX_DP

I
I

Intel QuickPath Interconnect received clock is the input clock that corresponds 

to Intel QuickPath Interconnect 1 port received data.

QPI1_CLKTX_DN
QPI1_CLKTX_DP

O
O

Intel QuickPath Interconnect forwarded clock sent with Intel QuickPath 

Interconnect port1 outbound data.

QPI1_COMP

I

Must be terminated on the system board using precision resistor.

QPI1_DRX_DN[19:0]
QPI1_DRX_DP[19:0]

I

I

QPI1_DRX_DN[19:0] and QPI1_DRX_DP[19:0] comprise the differential 

receive data for Intel QuickPath Interconnect port1. The inbound 20 lanes are 

connected to another component’s outbound lanes.

QPI1_DTX_DN[19:0]
QPI1_DTX_DP[19:0]

O

O

QPI1_DTX_DN[19:0] and QPI1_DTX_DP[19:0] comprise the differential 

transmit data for Intel QuickPath Interconnect port1. The outbound 20 lanes 

are connected to another component’s inbound lanes.