IBM Intel Xeon E5606 49Y3772 User Manual
Product codes
49Y3772
Electrical Specifications
56
Intel
®
Xeon
®
Processor 5600 Series Datasheet Volume 1
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
Not 100% tested. Specified by design characterization.
3.
It is recommended that TMS be asserted while TRST# is being deasserted.
Notes:
1.
Platform support for VID transitions is required for the processor to operate within specifications.
2.9
Processor AC Timing Waveforms
The following figures are to be used in conjunction with the AC specifications included
in
in
through
Note:
, the following apply:
1. All System Reference Clock signal AC specifications are referenced to the Crossing
Voltage (V
CROSS
) of the BCLK_DP and BCLK_DN at rising edge of BCLK_DP.
2. All TAP signal group AC specifications are referenced to the TCK at 0.5 * V
TT
at the
processor lands. All TAP signal group timings (TMS, TDI, and so forth) are
referenced at 0.5 * V
referenced at 0.5 * V
TT
at the processor die (pads).
3. All CMOS signal AC specifications are referenced at 0.5 * V
TT
at the processor
lands.
The Intel QuickPath Interconnect electrical test setup are shown in
and
Table 2-27. TAP Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1,2,3
TCK Period
31.25
ns
T
s
: TDI, TMS Setup Time
1
ns
T
h
: TDI, TMS Hold Time
1
ns
T
x
: TDO Clock to Output Delay
0.5
4
ns
T
q
: TRST# Assert Time
2
T
TCK
Table 2-28. VID Signal Group AC Specifications
T# Parameter
Min
Max
Unit
Figure
Notes
1
Ta: VID Step Time
1.25
µs
Tb: VID Down Transition to Valid V
CC
(min)
0
µs
Tc: VID Up Transition to Valid V
CC
(min)
15
µs
Td: VID Down Transition to Valid V
CC
(max)
15
µs
Te: VID Up Transition to Valid V
CC
(max)
0
µs