IBM Intel Xeon E5606 49Y3772 User Manual

67

Data transfer requires the clean reception of data and clock signals. Ringing below 
receiver thresholds, non-monotonic signal edges, and excessive voltage swings will 
adversely affect system timings. Ringback and signal non-monotonicity cannot be 
tolerated since these phenomena may inadvertently advance receiver state machines. 
Excessive signal swings (overshoot and undershoot) are detrimental to silicon gate 
oxide integrity, and can cause device failure if absolute voltage limits are exceeded. 
Overshoot and undershoot can also cause timing degradation due to the build up of 
inter-symbol interference (ISI) effects. 

For these reasons, it is crucial that the designer work towards a solution that provides 
acceptable signal quality across all systematic variations encountered in volume 
manufacturing.

This section documents signal quality metrics used to derive topology and routing 
guidelines through simulation. All specifications are specified at the processor die (pad 
measurements).

Specifications for signal quality are for measurements at the processor core only and 
are only observable through simulation. Therefore, proper signal simulation is the only 
means of properly verifying timing and signal quality requirements.

Overshoot (or undershoot) is the absolute value of the maximum voltage above or 
below V

SS

. The overshoot/undershoot specifications limit transitions beyond V

CCIO

 or 

V

SS

 due to the fast signal edge rates. The processor can be damaged by single and/or 

repeated overshoot or undershoot events on any input, output, or I/O buffer if the 
charge is large enough (that is, if the over/undershoot is great enough). Baseboard 
designs which meet signal integrity and timing requirements and which do not exceed 
the maximum overshoot or undershoot limits will insure reliable IO performance for the 
lifetime of the processor.

The pulse magnitude, duration, and activity factor must all be used to determine if the 
overshoot/undershoot pulse is within specifications.

Oscillations below the reference voltage cannot be subtracted from the total 

overshoot/undershoot pulse duration.

1.

These specifications are measured at the processor pin.

2.

Refer to 

 for description of Overshoot/Undershoot magnitude and duration.

Intel



 QuickPath Interconnect

-0.1 * V

TT

1.2 * V

TT

500 ps

DDR3

-0.1 * V

DDQ

1.2 * V

DDQ

0.5 * T

CH

Processor Sideband Signals

-0.1 * V

TT

1.2 * V

TT

50 ns

System Reference Clock

-0.3

1.15

NA