Intel E7-4850 AT80615007449AA User Manual

Product codes
AT80615007449AA
Page of 34
Intel
®
 Xeon
®
 Processor E7-8800/4800/2800 Product Families
13
Specification Update
 September 2012
Mixing Processor Within MP Platforms
Intel supports multiprocessor (MP) configurations consisting of processors:
1. From the same power optimization segment. 
2. That support the same maximum Intel
®
 QuickPath Interconnect (Intel
®
 QPI) and 
DDR3 memory speeds.
3. That share symmetry across physical packages with respect to the number of 
logical processors per package, number of cores per package, number of 
Intel
®
 QPI interfaces, and cache topology.
4. That have identical Extended Family, Extended Model, Processor Type, Family Code, 
and Model Number as indicated by the function 1 of the CPUID instruction.
Note:
Connected processors must operate with the same Intel
®
 QPI and core frequency.
While Intel does nothing to prevent processors from operating together, some 
combinations may not be supported due to limited validation, which may result in 
uncharacterized errata. Coupling this fact with the large number of Intel
®
 Xeon
®
 
Processor E7-8800/4800/2800 Product Families attributes, the following population 
rules and stepping matrix have been developed to define supported configurations.
1. Processors must be of the same power-optimization segment. This ensures 
processors include the same maximum Intel
®
 QPI and cache sizes.
2. Processors must operate at the same core frequency. Note: Processors within the 
same power-optimization segment supporting different maximum core frequencies 
(for example, a 2.26 GHz / 130 W and 2.00 GHz / 130 W) can be operated within a 
system. However, both must operated at the highest frequency rating commonly 
supported. Mixing components operating at different internal clock frequencies is 
not supported and will not be validated by Intel.
3. Processors must share symmetry across physical packages with respect to the 
number of logical processors per package, number of Intel
®
 QPI interfaces, and 
cache topology.
4. Mixing dissimilar steppings is only supported with processors that have identical 
Extended Family, Extended Model, Processor type, Family Code, and Model Number 
as indicated by the function 1 of the CPUID instruction. Mixing processors of 
different steppings but the same model (as per CPUID instruction) is supported. 
Details regarding the CPUID instruction are provided in the AP-487, Intel® 
Processor Identification and the CPUID Instruction application note and Intel® 64 
and IA-32 Architectures Software Developer’s Manual, Volume 2A.
5. After ANDing the feature flag and extended feature flag from the installed 
processors, any processor whose set of feature flags exactly matches the ANDed 
feature flags can be selected by the BIOS as the BSP. If no processor exactly 
matches the ANDed feature flag values, then the processors with the numerically 
lower CPUID should be selected as the BSP.
6. Intel requires that the processor microcode update be loaded on each processor 
operating within the system. Any processor that does not have the proper 
microcode update loaded is considered by Intel to be operating out of specification.
7. The workarounds identified in this, and subsequent specification updates, must 
properly applied to each processor in the system. Certain errata are specific to the 
multiprocessor environment. Errata for all processor steppings will affect system 
performance if not properly worked around.
8. Customers are fully responsible for the validation of their system configurations.