IBM Intel Xeon E5620 49Y3773 User Manual

65

In order In order to ensure Timestamp Counter (TSC) synchronization across sockets in multi-socket 

systems, the RESET# deassertion edge should arrive at the same BCLK rising edge at both sockets and 

should meet the Tsu and Th requirement of 600ps relative to BCLK, as outlined in 

.

This waveform illustrates an example of an Intel Adaptive Thermal Monitor transition or an Intel 

Enhanced SpeedStep Technology transition that is six VID step down from the current state and six 

steps back up. Any arbitrary up or down transition can be generalized from this waveform.