Gemalto M2M GmbH MC56 User Manual

Page of 104
MC55/56 Hardware Interface Description 
Confidential / Preliminary 
s
 
MC55/56_hd_v03.00 
Page 29 of 104 
16.08.2005 
Assertion of CTS indicates that the module is ready to receive data from the host application. 
In addition, if configured to a fixed bit rate (AT+IPR≠0), the module will send the URC 
“^SYSSTART” which notifies the host application that the first AT command can be sent to 
the module. The duration until this URC is output varies with the SIM card and may take a 
couple of seconds, particularly if the request for the SIM PIN is deactivated on the SIM card.  
 
Please note that no “^SYSSTART” URC will be generated if autobauding (AT+IPR=0) is 
enabled.  
 
To allow the application to detect the ready state of the module we recommend using 
hardware flow control which can be set with AT\Q or AT+ICF (see [1] for details). The default 
setting of MC55/56 is AT\Q0 (no flow control) which shall be altered to AT\Q3 (RTS/CTS 
handshake). If the application design does not integrate RTS/CTS lines the host application 
shall wait at least for the “^SYSSTART” URC. However, if the URCs are neither used (due to 
autobauding) then the only way of checking the module’s ready state is polling. To do so, try 
to send characters (e.g. “at”) until the module is responding. 
 
3.3.1.2 
Timing of the ignition process 
When designing your application platform take into account that powering up MC55/56 
requires the following steps. 
•  The ignition line cannot be operated until V
BATT+ 
passes the level of 3.0V. 
•  The ignition line shall not be operated earlier than 10ms after the last falling edge of VDD. 
•  10ms after V
BATT+ 
has reached 3.0V the ignition line can be switched low. The duration of 
the falling edge must not exceed 1ms. 
•  Another 100ms are required to power up the module.  
•  Ensure that V
BATT+ 
 does not fall below 3.0V while the ignition line is driven. Otherwise the 
module cannot be activated.  
•  If the VDDLP line is fed from an external power supply as explained in Chapter 3.8, the 
/IGT line is HiZ before the rising edge of BATT+. 
Figure 4: Timing of power-on process if VDDLP is not used 
 
3.0V
0V
BATT+
min. 100ms
max. 1ms
10ms
/IGT
HiZ
HiZ