Intel E7-2820 AT80615007245AA User Manual

18

Intel

®

 Xeon

®

 Processor E7-8800/4800/2800 Product Families

September 2012

Specification Update

Problem:

When home agent failover count saturation occurs, the memory controller signals a 

spurious CMCI (Corrected Machine Check Interrupt) without logging an error. Failover 

count saturation is not an error and a CMCI should not be issued.

Implication:

Due to this erratum, software receives a CMCI with no error logged.

Workaround:

None identified.

Status:

For the steppings affected, see the 

Problem:

If an uncorrectable memory controller error is followed by a software recoverable error, 

the memory controller will not set the S (Signaling flag) bit of the MCi_STATUS to 

indicate that a software recoverable error occurred. 

Implication:

Due to this erratum, the MCi_STATUS of the memory controller will have the fields 

Valid=1, UC=1, PCC=0, OVER=1 and S=0 logged. When the MCA handler comes in, it 

ignores the MCi_STATUS since S=0; and the MCA is treated as a spurious MCA.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the 

Problem:

When an explicit LLC (Last Level Cache) write-back software recoverable error is 

detected while there is already a poison error in the MCi_STATUS register, a machine 

check is signaled but the MCi_STATUS.S (Signaling Flag) bit is not set. In this case the 

MCi_STATUS.PCC (Processor Context Corrupt) bit and the S bit are both 0. As a result, 

the machine check handler assumes this to be a spurious error. 

Implication:

If there is already a poison error in the MCi_STATUS register and an LLC recoverable 

error is then logged the MCA handler may assume this to be a spurious error.

Workaround:

It is possible for the BIOS to contain a workaround for this erratum.

Status:

For the steppings affected, see the 

Problem:

Due to the processor not having a mechanism to detect incorrect alert frames, 

correctable SB (South Bound) CRC Error may be propagated to an uncorrected ECC 

error.

Implication:

An incorrect alert frame will not be detected by the processor. In most cases there is no 

issue, due to the memory buffer issuing a series of alert frames. In a specific case 

where an SB Intel

®

 Scalable Memory Interconnect (Intel

®

 SMI) CRC error (transient or 

persistent) is detected and the NB (North Bound) Alert frame responding to this error is 

also corrupted by an error, the original packet may not be reissued. However, since the 

memory controller uses two Intel

®

 SMI channels in lockstep for each cache line access, 

on a future read if one channel was affected by this issue the other would return valid 

data. Due to this erratum, the correctable SB CRC error may get propagated to be a 

detected but uncorrected ECC error. Intel has not observed this erratum on any 

commercially available system.

Workaround:

None identified.

Status:

For the steppings affected, see the