Intel E7-2803 AT80615006438AB User Manual
Product codes
AT80615006438AB
Power Management Architecture (Wbox)
48
Datasheet Volume 2 of 2
a. Messages initiated in response to a PMReq message from another node that
indicates the deepest state that this node will permit the originating node to
enter.
enter.
3. Inbound PMReq messages:
a. Requests from other node(s) for permission to transition to a deeper state, or
b. Announcements from other nodes that they have transitioned to a shallower
b. Announcements from other nodes that they have transitioned to a shallower
state.
4. Inbound CmpD messages:
a. Responses from other node(s) to a PMReq message from this node.
9.6
S-State Support
9.6.1
Overview
In ACPI terminology, S-states refer to system sleeping states. The Intel Xeon Processor
E7-8800/4800/2800 Product Families support S0, S4 and S15.
E7-8800/4800/2800 Product Families support S0, S4 and S15.
Note:
The Intel Xeon Processor E7-8800/4800/2800 Product Families do not support S1
(standalone), S1 with self refresh, and S3 states.
9.7
APIC Timer
The Intel Xeon processor 7500 series when in sleep state C3 and lower, or undergoing
ratio transition, the APIC timer stops running.
ratio transition, the APIC timer stops running.
For Intel Xeon Processor E7-8800/4800/2800 Product Families the APIC timer is always
running even during sleep state C3 and C6.
running even during sleep state C3 and C6.
9.8
PECI Sideband P-state Control
9.8.1
Overview
Intel Xeon Processor E7-8800/4800/2800 Product Families have added support for
sideband P-state control (limit) through PECI mailbox. Intel Xeon Processor E7-8800/
4800/2800 Product Families have also added support for two new request types P-state
Write and P-State Read in mailbox. Behavior and implementation details for both these
request types are discussed below.
sideband P-state control (limit) through PECI mailbox. Intel Xeon Processor E7-8800/
4800/2800 Product Families have also added support for two new request types P-state
Write and P-State Read in mailbox. Behavior and implementation details for both these
request types are discussed below.
9.8.2
MAILBOX_WRITE_P_STATE_LIMIT (request type = 0x23)
This command (MbxSend with above request type) provides the sideband P-state limit
to the OS requested P-states. The ratio resolution for the OS P-state on package is
done as usual considering various factors voting right and so forth. The sideband P-
state limit is finally applied on top of OS requested resolved P-state (depending on the
package current operating state, it may or may not lead to P-state transition).
to the OS requested P-states. The ratio resolution for the OS P-state on package is
done as usual considering various factors voting right and so forth. The sideband P-
state limit is finally applied on top of OS requested resolved P-state (depending on the
package current operating state, it may or may not lead to P-state transition).
Intel Xeon Processor E7-8800/4800/2800 Product Families design supports all clock
ratios between MaxNonTurboRatio (P1) and MaxEfficiencyRatio(Pn) as allowable P-state
request but it may expose only selective clock ratios as valid P-state in ACPI table. Intel
Xeon Processor E7-8800/4800/2800 Product Families supports minimum three OS
requested P-states P0 (assuming turbo is enabled), P1 and Pn.
ratios between MaxNonTurboRatio (P1) and MaxEfficiencyRatio(Pn) as allowable P-state
request but it may expose only selective clock ratios as valid P-state in ACPI table. Intel
Xeon Processor E7-8800/4800/2800 Product Families supports minimum three OS
requested P-states P0 (assuming turbo is enabled), P1 and Pn.