Intel E7-2803 AT80615006438AB User Manual

Product codes
AT80615006438AB
Page of 50
Datasheet Volume 2 of 2
7
Introduction
1
Introduction
The Intel
®
 Xeon
®
 Processor E7-8800/4800/2800 Product Families is the second-
generation chip multiprocessor (CMP) offering Intel
®
 QuickPath Interconnect (Intel
®
 
QPI) technology in the Intel
®
 Xeon
®
 MP processor family of processors. The Intel Xeon 
Processor E7-8800/4800/2800 Product Families implement up to ten multi-threaded 
(two thread) cores based upon the Intel Xeon Processor E7-8800/4800/2800 Product 
Families core design. A large, up to 30 MB, last-level cache (level 3), has been 
implemented to be shared across all active cores. The Intel Xeon Processor E7-8800/
4800/2800 Product Families implement Intel QuickPath Interconnect technology to 
replace the traditionally-implemented front-side bus. The Intel Xeon Processor E7-
8800/4800/2800 Product Families provides four full width Intel QuickPath Interconnect 
links, sufficient to implement a glue-less (direct connect) four-processor socket and 
two IOH solutions, as well as scalable solutions based on OEM-developed external node 
controllers (referred to as XNC). The Intel Xeon Processor E7-8800/4800/2800 Product 
Families also integrate two memory controllers supporting DDR3 memory technology to 
further enhance memory latency at higher memory capacity. The Intel Xeon Processor 
E7-8800/4800/2800 Product Families will be implemented on Intel 32-nm process 
technology and will be binary-compatible with applications running on previous 
members of Intel's IA-32/IA-64 microprocessors.
1.1
Intel
®
 Xeon
®
 Processor E7-8800/4800/2800 
Product Families Features
New features of the Intel Xeon Processor E7-8800/4800/2800 Product Families include:
• Chip multiprocessor architecture with up to ten cores per socket
• Hyper-threaded cores, two threads
• Low-power, high-performance Intel Xeon Processor E7-8800/4800/2800 Product 
Families Core architecture
• Supports 48-bit virtual addressing and 44-bit physical addressing
• 32 KB Level 1 instruction cache with single bit error correction, and L1 Data cache: 
32-KB Level 1 data cache with parity protection, or 16 KB Level 1 with ECC error 
correction and detection on data and on TAG
• 256 kB L2 instruction/data cache, ECC protected (SECDED)
• 30-MB LLC, instruction/data cache, ECC protected (Double Bit Error Correction, 
Triple bit Error Detection(DECTED), and SECDEC on TAG)
• High-bandwidth point-to-point Intel QuickPath Interconnect link interface enabling 
glueless 4-socket MP platforms:
— Four full width Intel QuickPath Interconnect links targeted at 4.8–6.4 GT/s 
— Aggregate bandwidth of 25.6 GB/s per Intel QuickPath Interconnect link
(at 6.4 GT/s)
• Two on-chip memory controllers provide ample memory bandwidth and memory 
capacity for demanding enterprise applications:
— Each memory controller manages two Intel
®
 Scalable Memory Interconnect 
(Intel
®
 SMI) channels, operated in lockstep, and a Intel
®
 7500 Scalable 
Memory Buffer, an Intel SMI-DDR3 bridge, on each Intel SMI channel. 
— Total of four Intel SMI channels