IBM Intel Xeon E5606 49Y3775 User Manual

33

1. Unless otherwise noted, all specifications in this table apply to all processors.

2. Individual processor VID and/or VTT_VID values may be calibrated during manufacturing such that two 

devices at the same speed may have different settings.

3. These voltages are targets only. A variable voltage source should exist on systems in the event that a 

different voltage is required.

4. The V

CC

 voltage specification requirements are measured across vias on the platform for the VCCSENSE and 

VSSSENSE pins close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe 

capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be 

less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

5. The V

TT 

voltage specification requirements are measured across vias on the platform for the VTTD_SENSE 

and VSS_SENSE_VTTD lands close to the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum 

probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should 

be less than 5 mm. Ensure external noise from the system is not coupled in the scope probe.

6. Refer to 

 and corresponding 

. The processor should not be subjected to any static V

CC

 

level that exceeds the V

CC_MAX

 associated with any particular current. Failure to adhere to this specification 

can shorten processor lifetime.

7. Minimum V

CC

 and maximum I

CC

 are specified at the maximum processor case temperature (T

CASE

) shown in 

. I

CC_MAX

 is specified at the relative V

CC_MAX

 point on the V

CC

 load line. The processor is capable of 

drawing I

CC_MAX

 for up to 10 ms. Refer to 

 through 

 for further details on the average 

processor current draw over various time durations.

8. Refer to 

 and corresponding 

. The processor should not be subjected to any static V

TT

 

level that exceeds the V

TT_MAX

 associated with any particular current. Failure to adhere to this specification 

can shorten processor lifetime.

9. This specification represents the V

CC

 reduction due to each VID transition. See 

. AC timing 

requirements for VID transitions are included in 

10.Baseboard bandwidth is limited to 20 MHz.

11.FMB is the flexible motherboard guidelines. See 

 for FMB details.

12.ICC_TDC (Thermal Design Current) is the sustained (DC equivalent) current that the processor is capable of 

drawing indefinitely and should be used for the voltage regulator temperature assessment. The voltage 

regulator is responsible for monitoring its temperature and asserting the necessary signal to inform the 

processor of a thermal excursion.

I

CC_TDC

I

CCPLL_TDC

I

DDQ_TDC

I

TT_TDC

Thermal Design 

Current:
Frequency Optimized 

Server/Workstation
(TDP = 130 W)
(Launch - FMB)

V

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

110

1.1

9
6

22

A
A
A
A
A

11,12

Thermal Design 

Current: 

Advanced 

Server/Workstation

(TDP = 95 W)
(Launch - FMB)

V

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

101

1.1

9
6

22

A
A
A
A
A

11,12

Thermal Design 

Current: 

Standard 

Server/Workstation

(TDP = 80 W)
(Launch - FMB)

V

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

70

1.1

9
6

22

A
A
A
A
A

11,12

Thermal Design 

Current: 

Low Power & LV-60W

(TDP = 60 W)
(Launch - FMB)

V

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

60

1.1

9
6

20

A
A
A
A
A

11,12

Thermal Design 

Current: 

Low Power & LV-40W

(TDP = 40 W)
(Launch - FMB)

V

CC

V

CCPLL

V

DDQ

V

TTA

V

TTD

40

1.1

9
6

20

A
A
A
A
A

11,12

I

DDQ_S3

DDR3 System Memory 

Interface Supply 

Current in Standby 

State

V

DDQ

1

A

13,14