Intel E7-4807 AT80615006432AB User Manual
Product codes
AT80615006432AB
Memory Controller (Mbox)
32
Datasheet Volume 2 of 2
Note:
Memory Mirroring with tracker mode 6 is not supported.
Note:
RFR_FSM errors may be logged in the Mbox while in 2x refresh.
7.3
Double Device Data Correction (DDDC)
DDDC (Double Device Data Correction) is a feature which assures data availability after
hard failure of 2 x4 DRAM’s.
hard failure of 2 x4 DRAM’s.
Supports x4 DDDC plus an additional single bit error correction.
7.3.1
DDDC flow overview
• One x4 DRAM device in each rank is reserved as spare device.
• ECC code has parity nibble instead of parity byte. This way DDDC ECC code has 16
• ECC code has parity nibble instead of parity byte. This way DDDC ECC code has 16
bits of parity instead of 32 bits in regular ECC code.
• When first device failure is detected, content of failing/failed device gets read,
corrected, and then written back in spare device.
• When second device failure is detected, the failed device number is logged and
regular device recovery process is followed.
7.3.2
DDDC Constraints
• DDDC can be enabled by BIOS only and only if x4 DIMMs are populated behind the
memory controller. If x4 and x8 DIMMs are mixed together, DDDC should be
disabled.
disabled.
• Double strike errors are not corrected when DDDC is enabled.
• DDDC should be disabled on memory controller that is a Mirror Master.
• DDDC should be disabled on memory controller that is a Mirror Master.
7.4
Leaky Bucket Error Counters
This feature is to make the error counters counting the more transient errors, to be
more accurate. The counters which are selected to be leaky bucket in nature are given
below with the reasoning.
more accurate. The counters which are selected to be leaky bucket in nature are given
below with the reasoning.
7.4.1
Per Rank Memory Error Counter
This counter counts the DRAM errors per rank.There are possibilities for this counter to
count transient errors as memory errors. To make it accurate we can make them as
leaky bucket counters.
count transient errors as memory errors. To make it accurate we can make them as
leaky bucket counters.
7.4.2
Error Flow Counters
• SB soft reset flow, SB Fast reset flow, NB Transient error, NB soft reset flow, NB
Fast reset flow counters.
• These counters count the number of time each flow is run and how consistent they
are. For example, NB soft reset flow is consistent it triggers NB fast reset flow. If
NB fast reset flow is consistent it declares lane dead.
NB fast reset flow is consistent it declares lane dead.
• To make these consistency check very accurate, currently an nearly leaky bucket
kind of counter is implemented. That can be converted as regular leaky bucket
counters.
counters.