Intel E7-4807 AT80615006432AB User Manual
Product codes
AT80615006432AB
Datasheet Volume 2 of 2
45
Power Management Architecture (Wbox)
defaults to having a sub-state of zero. However, I/O redirected MWAITs always
assumes the 'break on IF=0' control that can be selected using ECX=1 with an MWAIT
instruction.
assumes the 'break on IF=0' control that can be selected using ECX=1 with an MWAIT
instruction.
9.2.2.7
Core C3 Auto Demote
The operating system requests entry to a specific C-state by supplying the appropriate
hint with the MWAIT instruction. If the hint supplied is not supported by the processor,
the thread will request a transition to the next higher power C-state that is supported
by the part. For example, if the OS executed MWAIT with a C9 hint on Intel Xeon
Processor 7500 Series, this would be translated to a C6 request on that specific thread.
Any sub-state requests that originally existed will be kept even if clipping takes effect.
hint with the MWAIT instruction. If the hint supplied is not supported by the processor,
the thread will request a transition to the next higher power C-state that is supported
by the part. For example, if the OS executed MWAIT with a C9 hint on Intel Xeon
Processor 7500 Series, this would be translated to a C6 request on that specific thread.
Any sub-state requests that originally existed will be kept even if clipping takes effect.
9.3
Core C6 Support
Core C6 is a new power state for the Intel Xeon Processor E7-8800/4800/2800 Product
Families.
Families.
9.3.1
Core C6
9.3.1.1
Introduction
As deeper ACPI C-states are reached, leakage power becomes the only remaining
source of power in the processor cores. The ideal low power C-state drives the power of
the core to 0. The goal of the C6 state is to eliminate leakage power by completely
removing voltage from a core or cores.
source of power in the processor cores. The ideal low power C-state drives the power of
the core to 0. The goal of the C6 state is to eliminate leakage power by completely
removing voltage from a core or cores.
Before voltage can be removed from a core in C6, it is required to save all processor
state relevant to the processor context in an area which can later be accessed to
restore state and resume operation. This requires a save area which will not be
powered down. On Intel Xeon Processor E7-8800/4800/2800 Product Families a
dedicated C6 SRAM is used to store core state on entry to C6.
state relevant to the processor context in an area which can later be accessed to
restore state and resume operation. This requires a save area which will not be
powered down. On Intel Xeon Processor E7-8800/4800/2800 Product Families a
dedicated C6 SRAM is used to store core state on entry to C6.
9.3.1.2
Thread / Core C6 Entry / Exit
C6 entry can occur on execution of an MWAIT instruction with a C6 argument, or via an
I/O read from the P_LVL3 address.
I/O read from the P_LVL3 address.
9.3.2
Core C6 Entry/Exit Flow
A thread enters C6 via one of two mechanisms:
•
•
"MWAIT(C6) -
•
"I/O redirection - An I/O read to an address base and range specified in the
PMG_IO_CAPTURE MSR (0x0E4) is instead redirected to the MWAIT flow
PMG_IO_CAPTURE MSR (0x0E4) is instead redirected to the MWAIT flow
.
Core remains in the C6 until it receives break events (interrupts).
9.4
Package C6 Support
Package C6 is a new power state for the Intel Xeon Processor E7-8800/4800/2800
Product Families.
Product Families.