Intel E3-1220L CM8062307262828 User Manual
Product codes
CM8062307262828
Technologies
42
Datasheet, Volume 1
3.5
Intel
®
Advanced Vector Extensions (AVX)
Intel
®
Advanced Vector Extensions (AVX) is the latest expansion of the Intel instruction
set. It extends the Intel
®
Streaming SIMD Extensions (SSE) from 128-bit vectors into
256-bit vectors. Intel AVX addresses the continued need for vector floating-point
performance in mainstream scientific and engineering numerical applications, visual
processing, recognition, data-mining/synthesis, gaming, physics, cryptography and
other areas of applications. The enhancement in Intel AVX allows for improved
performance due to wider vectors, new extensible syntax, and rich functionality
including the ability to better manage, rearrange, and sort data. For more information
on Intel AVX, see
performance in mainstream scientific and engineering numerical applications, visual
processing, recognition, data-mining/synthesis, gaming, physics, cryptography and
other areas of applications. The enhancement in Intel AVX allows for improved
performance due to wider vectors, new extensible syntax, and rich functionality
including the ability to better manage, rearrange, and sort data. For more information
on Intel AVX, see
http://www.intel.com/software/avx
3.6
Advanced Encryption Standard New Instructions
(AES-NI)
(AES-NI)
The processor supports Advanced Encryption Standard New Instructions (AES-NI) that
are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast and
secure data encryption and decryption based on the Advanced Encryption Standard
(AES). AES-NI are valuable for a wide range of cryptographic applications; such as,
applications that perform bulk encryption/decryption, authentication, random number
generation, and authenticated encryption. AES is broadly accepted as the standard for
both government and industry applications, and is widely deployed in various protocols.
are a set of Single Instruction Multiple Data (SIMD) instructions that enable fast and
secure data encryption and decryption based on the Advanced Encryption Standard
(AES). AES-NI are valuable for a wide range of cryptographic applications; such as,
applications that perform bulk encryption/decryption, authentication, random number
generation, and authenticated encryption. AES is broadly accepted as the standard for
both government and industry applications, and is widely deployed in various protocols.
AES-NI consists of six Intel
®
SSE instructions. Four instructions, AESENC,
AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES encryption and
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for
supporting AES, offering security, high performance, and a great deal of flexibility.
decryption. The other two, AESIMC and AESKEYGENASSIST, support the AES key
expansion procedure. Together, these instructions provide a full hardware for
supporting AES, offering security, high performance, and a great deal of flexibility.
3.6.1
PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
3.7
Intel
®
64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture that provides a key mechanism
for interrupt delivery. This extension is intended primarily to increase processor
addressability.
for interrupt delivery. This extension is intended primarily to increase processor
addressability.
Specifically, x2APIC:
Retains all key elements of compatibility to the xAPIC architecture
delivery modes
interrupt and processor priorities
interrupt sources
interrupt destination types