Intel i5-2390T CM8062301002115 User Manual
Product codes
CM8062301002115
Power Management
54
Datasheet, Volume 1
Selection of power modes should be according to power-performance or thermal trade-
offs of a given system:
• When trying to achieve maximum performance and power or thermal consideration
is not an issue: use no power-down.
• In a system that tries to minimize power-consumption, try to use the deepest
power-down mode possible – DLL-off or APD_DLLoff.
• In high-performance systems with dense packaging (that is, complex thermal
design) the power-down mode should be considered in order to reduce the heating
and avoid DDR throttling caused by the heating.
and avoid DDR throttling caused by the heating.
Control of the power-mode through CRB-BIOS: The BIOS selects by default no-power-
down. There are knobs to change the power-down selected mode.
Another control is the idle timer expiration count. This is set through PM_PDWN_config
bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the MC will have more
opportunities to put DDR in power-down. The minimum recommended value for this
register is 15. There is no BIOS hook to set this register. Customers who choose to
change the value of this register can do it by changing the BIOS. For experiments, this
register can be modified in real time if BIOS did not lock the MC registers.
Note:
In APD, APD-PPD, and APD-DLLoff there is no point in setting the idle-counter in the
same range of page-close idle timer.
Another option associated with CKE power-down is the S_DLL-off. When this option is
enabled, the SBR I/O slave DLLs go off when all channel ranks are in power-down. (Do
not confuse it with the DLL-off mode, in which the DDR DLLs are off). This mode
requires to define the I/O slave DLL wakeup time.
enabled, the SBR I/O slave DLLs go off when all channel ranks are in power-down. (Do
not confuse it with the DLL-off mode, in which the DDR DLLs are off). This mode
requires to define the I/O slave DLL wakeup time.
4.3.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during power-
up. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
configuration register. Using this method, CKE is ensured to remain inactive for much
longer than the specified 200 micro-seconds after power and clocks to SDRAM devices
are stable.
4.3.2.2
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package C3 and C6 low-power states. RMPM functionality depends
on the graphics/display state (relevant only when processor graphics is being used), as
well as memory traffic patterns generated by other connected I/O devices. The target
behavior is to enter self-refresh as long as there are no memory requests to service.
When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh, the
processor core flushes pending cycles and then enters all SDRAM ranks into self-
refresh. The CKE signals remain LOW so the SDRAM devices perform self-refresh.