Ability Enterprise Co. Ltd. AA1D1 User Manual
802.11b/g/n Wireless LAN Daughter board V2.1
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17
GSPI Timing
Parameter
Symbol
Minimum
Maximum
Units Note
Clock period
T1
20.8
-
ns
Fmax= 48 MHz
Clock high/low
T2/T3
(0.45xT1) -
T4
(0.55 xT1) -T4
ns
ns
-
Clock rise/fall time
T4/T5
-
2.5
ns
-
Input setup time
T6
5
-
ns
Setup time, SIMO valid to SPI_CLK active
edge
edge
Input hold time
T7
5
-
ns
Hold time, SPI_CLK active edge to SIMO
invalid
invalid
Output setup time
T8
5
-
ns
Setup time, SOMI valid before SPI_CLK
rising
rising
Output hold time
T9
5
-
ns
Hold time, SPI_CLK active edge to SOMI
invalid
invalid
CSX to clocka
-
7.86
-
ns
CSX fall to 1st rising edge
Clock to CSXa
-
-
-
ns
Last falling edge to CSX high
a.SPI_CSx remains active for entire duration of SPI read/write/write_read transaction (i.e.,
overall words for multiple word transaction)
overall words for multiple word transaction)
Sleep mode
The radio, AFE, PLLS, and the crystal oscillator are powered down. The rest of the module
remains powered up in an IDLE state. All main clocks are shut down. The 32.768 kHz LPO
sleep clock is available only for the PMU sequencer. This condition is necessary to allow the
PMU sequencer to wake up the chip and transition to Active mode. In Sleep mode, the primary
power consumed is due to leakage current.
remains powered up in an IDLE state. All main clocks are shut down. The 32.768 kHz LPO
sleep clock is available only for the PMU sequencer. This condition is necessary to allow the
PMU sequencer to wake up the chip and transition to Active mode. In Sleep mode, the primary
power consumed is due to leakage current.