AMD Sempron™ Processor-In-a-Box 2500+ SDA2500BOX User Manual
Product codes
SDA2500BOX
Chapter 4
Power Management
13
31993A-1 September 2004
AMD Sempron™ Processor Model 10 Data Sheet
AMD Preliminary Information
interrupt for Halt or STPCLK# deassertion. Reconnect is
initiated by the Northbridge to probe the processor.
initiated by the Northbridge to probe the processor.
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
N o r t h b r i d g e a s s e r t s C L K F W D R S T i n a n t i c i p a t i o n o f
reestablishing a connection at some later point.
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
N o r t h b r i d g e a s s e r t s C L K F W D R S T i n a n t i c i p a t i o n o f
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this
are possible.
alternate chipset implementations that do not require this
are possible.
Note: In response to Halt special cycles, the Northbridge passes the
Halt special cycle to the PCI bus or Southbridge
immediately.
immediately.
The processor can receive an interrupt after it sends a Halt
special cycle, or STPCLK# deassertion after it sends a Stop
Gra nt s pecia l cy cle to the Nor thbridge but befo re the
disconnect actually occurs. In this case, the processor sends the
Connect spe cia l cycle to the Nor thbridge , rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
special cycle, or STPCLK# deassertion after it sends a Stop
Gra nt s pecia l cy cle to the Nor thbridge but befo re the
disconnect actually occurs. In this case, the processor sends the
Connect spe cia l cycle to the Nor thbridge , rather than
continuing with the disconnect sequence. In response to the
Connect special cycle, the Northbridge cancels the disconnect
request.
The system is required to assert the CONNECT signal before
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
returning the C-bit for the connect special cycle (assuming
CONNECT has been deasserted).
For more information, see the AMD Athlon™ and AMD Duron™
System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.
System Bus Specification, order# 21902 for the definition of the
C-bit and the Connect special cycle.