AMD Sempron™ Processor-In-a-Box 2800+ SDC2800BOX User Manual

Product codes
SDC2800BOX
Page of 102
40
Signal and Power-Up Requirements
Chapter 8
AMD Sempron™ Processor Model 10 Data Sheet
31993A-1 September 2004
AMD Preliminary Information
Power-Up Timing Requirements.  The signal timing requirements are 
as follows:
1. RESET# must be asserted before PWROK is asserted.
The AMD Sempron processor model 10 does not set the 
correct clock multiplier if PWROK is asserted prior to a 
RESET# assertion. It is recommended that RESET# be 
asserted at least 10 nanoseconds prior to the assertion of 
PWROK.
In practice, a Southbridge asserts RESET# milliseconds 
before PWROK is asserted.
2. All motherboard voltage planes must be within 
specification before PWROK is asserted.
PWROK is an output of the voltage regulation circuit on the 
motherboard. PWROK indicates that V
CC_CORE
 and all 
other voltage planes in the system are within specification.
The motherboard is required to delay PWROK assertion for 
a minimum of three milliseconds from the 3.3 V supply 
being within specification. This delay ensures that the 
system clock (SYSCLK/SYSCLK#) is operating within 
specification when PWROK is asserted.
The processor core voltage, V
CC_CORE
, must be within 
specification as dictated by the VID[4:0] pins driven by the 
processor before PWROK is asserted. Before PWROK 
assertion, the AMD Sempron processor is clocked by a ring 
oscillator. 
The processor PLL is powered by VCCA. The processor PLL 
does not lock if VCCA is not high enough for the processor 
logic to switch for some period before PWROK is asserted. 
VCCA must be within specification at least five 
microseconds before PWROK is asserted.
In practice VCCA, V
CC_CORE
, and all other voltage planes 
must be within specification for several milliseconds before 
PWROK is asserted.
After PWROK is asserted, the processor PLL locks to its 
operational frequency.
3. The system clock (SYSCLK/SYSCLK#) must be running 
before PWROK is asserted.
When PWROK is asserted, the processor switches from 
driving the internal processor clock grid from the ring 
oscillator to driving from the PLL. The reference system