Intel i7-2600 CM8062300834302S User Manual

Product codes
CM8062300834302S
Page of 296
Datasheet, Volume 2
129
Processor Configuration Registers
2.7.6
VC0RSTS—VC0 Resource Status Register
This register reports the Virtual Channel specific status.
2.7.7
PEG_TC—PCI Express Completion Time-out Register
This register reports PCI Express configuration control of PCI Express Completion Time-
out related parameters that are not required by the PCI Express specification.
B/D/F/Type:
0/1/0–2/MMR
Address Offset:
11A–11Bh
Reset Value:
0002h
Access:
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Bit
Attr
Reset 
Value
RST/
PWR
Description
15:2
RO
0h
Reserved
1
RO-V
1b
Uncore
VC0 Negotiation Pending (VC0NP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation 
(initialization or disabling).
This bit indicates the status of the process of Flow Control 
initialization. It is set by default on Reset, as well as whenever the 
corresponding Virtual Channel is Disabled or the Link is in the 
DL_Down state. It is cleared when the link successfully exits the 
FC_INIT2 state.
Before using a Virtual Channel, software must check whether the 
VC Negotiation Pending fields for that Virtual Channel are cleared 
in both Components on a Link.
0
RO
0h
Reserved
B/D/F/Type:
0/1/0–2/MMR
Address Offset:
208–20Bhh
Access:
RW
Bit
Attr
Reset 
Value
RST/
PWR
Description
31:15
RO
00000000
00000000
0b
Reserved
14:12
RW
111b
PCI Express Completion Time-out (PEG_TC)
This register determines the number of milliseconds the 
Transaction Layer will wait to receive an expected completion. To 
avoid hang conditions, the Transaction Layer will generate a 
dummy completion to the requestor if it does not receive the 
completion within this time period.
000 = Disable
001 = Reserved
010 = Reserved
100 = Reserved
101 = Reserved
110 = Reserved
x11 = 48 ms – for normal operation
11:0
RO
00000000
0000b
Reserved