Intel i7-2600 CM8062300834302S User Manual

146

Datasheet, Volume 2

6

RW

0b

Uncore

Parity Error Response Enable (PERRE)
Controls whether or not the Master Data Parity Error bit in the PCI 

Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be 

set.

1 = Master Data Parity Error bit in PCI Status register CAN be set.

5

RO

0b

Uncore

VGA Palette Snoop (VGAPS)
Not Applicable or Implemented. Hardwired to 0. 

4

RO

0b

Uncore

Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hardwired to 0. 

3

RO

0b

Uncore

Special Cycle Enable (SCE)
Not Applicable or Implemented. Hardwired to 0. 

2

RW

0b

Uncore

Bus Master Enable (BME)
Controls the ability of the PEG port to forward Memory Read/Write 

Requests in the upstream direction.
0 = This device is prevented from making memory requests to its 

primary bus. Note that according to PCI Specification, as MSI 

interrupt messages are in-band memory writes, disabling the 

bus master enable bit prevents this device from generating 

MSI interrupt messages or passing them from its secondary 

bus to its primary bus. Upstream memory writes/reads, peer 

writes/reads, and MSIs will all be treated as illegal cycles. 

Writes are aborted. Reads are aborted and will return 

Unsupported Request status (or Master abort) in its 

completion packet. 

1 = This device is allowed to issue requests to its primary bus. 

Completions for previously issued memory read requests on 

the primary bus will be issued when the data is available. This 

bit does not affect forwarding of Completions from the 

primary interface to the secondary interface.

1

RW

0b

Uncore

Memory Access Enable (MAE)
0 = All of device memory space is disabled.

1 = Enable the Memory and Pre-fetchable memory address ranges 

defined in the MBASE, MLIMIT, PMBASE, and PMLIMIT 

registers.

0

RW

0b

Uncore

IO Access Enable (IOAE)
0 = All of device I/O space is disabled.

1 = Enable the I/O address range defined in the IOBASE, and 

IOLIMIT registers.