Intel i7-2600 CM8062300834302S User Manual
Product codes
CM8062300834302S
Datasheet, Volume 2
193
Processor Configuration Registers
2.12.10 DMIVC1RSTS—DMI VC1 Resource Status Register
This register reports the Virtual Channel specific status.
2.12.11 DMIVCPRCAP—DMI VCp Resource Capability Register
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
26–27h
Reset Value:
0002h
Access:
RO-V
Size:
16 bits
BIOS Optimal Default
0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
15:2
RO
0h
Reserved
1
RO-V
1b
Uncore
Virtual Channel 1 Negotiation Pending (VC1NP)
0 = The VC negotiation is complete.
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation
(initialization or disabling).
Software may use this bit when enabling or disabling the VC. This
bit indicates the status of the process of Flow Control initialization.
It is set by default on Reset, as well as when the corresponding
Virtual Channel is Disabled or the Link is in the DL_Down state. It
is cleared when the link successfully exits the FC_INIT2 state.
Before using a Virtual Channel, software must check whether the
Before using a Virtual Channel, software must check whether the
VC Negotiation Pending fields for that Virtual Channel are cleared
in both Components on a Link.
0
RO
0h
Reserved
B/D/F/Type:
0/0/0/DMIBAR
Address Offset:
28–2Bh
Reset Value:
0000_0001h
Access:
RO
Size:
32 bits
BIOS Optimal Default
00h
Bit
Attr
Reset
Value
RST/
PWR
Description
31:24
RO
00h
Uncore
Reserved for Port Arbitration Table Offset (PATO)
23
RO
0h
Reserved
22:16
RO
00h
Uncore
Reserved for Maximum Time Slots (MTS)
15
RO
0b
Uncore
Reject Snoop Transactions (REJSNPT)
0 = Transactions with or without the No Snoop bit set within the
0 = Transactions with or without the No Snoop bit set within the
TLP header are allowed on this VC.
1 = Any transaction for which the No Snoop attribute is applicable
but is not set within the TLP Header will be rejected as an
Unsupported Request.
14:8
RO
0h
Reserved
7:0
RO
01h
Uncore
Reserved for Port Arbitration Capability (PAC)