Intel i7-2600 CM8062300834302S User Manual

236

Datasheet, Volume 2

This register specifies the fault event interrupt message control bits.

31

RW

1b

Uncore

Interrupt Mask (IM)
0 = No masking of interrupt. When an interrupt condition is 

detected, hardware issues an interrupt message (using the 

Fault Event Data and Fault Event Address register values).

1 = This is the value on reset. Software may mask interrupt 

message generation by setting this bit. Hardware is prohibited 

from sending the interrupt message when this bit is set.

30

RO-V

0h

Uncore

Interrupt Pending (IP)
Hardware sets the IP bit when it detects an interrupt condition, 

which is defined as:

• When primary fault logging is active, an interrupt condition 

occurs when hardware records a fault through one of the Fault 

Recording registers and sets the PPF bit in Fault Status 

register.

• When advanced fault logging is active, an interrupt condition 

occurs when hardware records a fault in the first fault record 

(at index 0) of the current fault log and sets the APF bit in the 

Fault Status register.

• Hardware detected error associated with the Invalidation 

Queue, setting the IQE bit in the Fault Status register.

• Hardware detected invalid Device-IOTLB invalidation 

completion, setting the ICE bit in the Fault Status register.

• Hardware detected Device-IOTLB invalidation completion time-

out, setting the ITE bit in the Fault Status register.

If any of the status fields in the Fault Status register was already 

Set at the time of setting any of these bits, it is not treated as a 

new interrupt condition.
The IP bit is kept set by hardware while the interrupt message is 

held pending. The interrupt message could be held pending due to 

interrupt mask (IM field) being Set or other transient hardware 

conditions.
The IP bit is cleared by hardware as soon as the interrupt message 

pending condition is serviced. This could be due to either:

• Hardware issuing the interrupt message due to either change 

in the transient hardware condition that caused interrupt 

message to be held pending, or due to 

• Software clearing the IM bit.

Software servicing all the pending interrupt status bits in the Fault 

Status register as follows:

• When primary fault logging is active, software clearing the 

Fault (F) bit in all the Fault Recording registers with faults, 

causing the PPF bit in Fault Status register to be evaluated as 

clear.

• Software clearing other status bit in the Fault Status register 

by writing back the value read from the respective bits.

29:0

RO

0h