Intel i7-2600 CM8062300834302S User Manual
Product codes
CM8062300834302S
Datasheet, Volume 2
35
Processor Configuration Registers
2.3.8
System Management Mode (SMM)
Unlike FSB platforms, the Core handles all SMM mode transaction routing. Also, the
platform no longer supports HSEG. The processor will never allow I/O devices access to
CSEG/TSEG/HSEG ranges.
platform no longer supports HSEG. The processor will never allow I/O devices access to
CSEG/TSEG/HSEG ranges.
DMI Interface and PCI Express masters are not allowed to access the SMM space.
2.3.9
SMM and VGA Access through GTT TLB
Accesses through the Graphics Translation Table (GTT) Translation Lookaside Buffer
(TLB) address translation SMM DRAM space are not allowed. Writes will be routed to
Memory address 000C_0000h with byte enables de-asserted and reads will be routed
to Memory address 000C_0000h. If a GTT TLB translated address hits SMM DRAM
space, an error is recorded in the PGTBL_ER register.
(TLB) address translation SMM DRAM space are not allowed. Writes will be routed to
Memory address 000C_0000h with byte enables de-asserted and reads will be routed
to Memory address 000C_0000h. If a GTT TLB translated address hits SMM DRAM
space, an error is recorded in the PGTBL_ER register.
PCI Express and DMI Interface originated accesses are never allowed to access SMM
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded in the PGTBL_ER register.
space directly or through the GTT TLB address translation. If a GTT TLB translated
address hits enabled SMM DRAM space, an error is recorded in the PGTBL_ER register.
PCI Express* and DMI Interface write accesses through GMADR range will not be
snooped. Only PCI Express* and DMI assesses to GMADR linear range (defined using
fence registers) are supported. PCI Express and DMI Interface tileY and tileX writes to
GMADR are not supported. If, when translated, the resulting physical address is to
enable SMM DRAM space, the request will be remapped to address 000C_0000h with
de-asserted byte enables.
snooped. Only PCI Express* and DMI assesses to GMADR linear range (defined using
fence registers) are supported. PCI Express and DMI Interface tileY and tileX writes to
GMADR are not supported. If, when translated, the resulting physical address is to
enable SMM DRAM space, the request will be remapped to address 000C_0000h with
de-asserted byte enables.
PCI Express and DMI Interface read accesses to the GMADR range are not supported,
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
therefore will have no address translation concerns. PCI Express and DMI Interface
reads to GMADR will be remapped to address 000C_0000h. The read will complete with
UR (unsupported request) completion status.
GTT fetches are always decoded (at fetch time) to ensure not in SMM (actually,
anything above base of TSEG or 640K–1M). Thus, they will be invalid and go to address
000C_0000h, but that is not specific to PCI Express or DMI; it applies to processor or
internal graphics engines.
anything above base of TSEG or 640K–1M). Thus, they will be invalid and go to address
000C_0000h, but that is not specific to PCI Express or DMI; it applies to processor or
internal graphics engines.
2.3.10
Intel
®
Management Engine (Intel
ME) Stolen Memory
Accesses
There are only 2 ways to legally access Intel ME stolen memory.
• PCH accesses mapped to VCm will be decoded to ensure only Intel ME stolen
memory is targeted. These VCm accesses will route non-snooped directly to DRAM.
This is the means by which the Intel ME engine (located within the PCH) is able to
access the Intel ME stolen range.
This is the means by which the Intel ME engine (located within the PCH) is able to
access the Intel ME stolen range.
• The Display engine is allowed to access Intel ME stolen memory as part of KVM
flows. Specifically, Display initiated HHP reads (for displaying a KVM frame) and
Table 2-3.
SMM regions
SMM Space Enabled
Transaction Address Space
DRAM Space (DRAM)
Compatible (C)
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
TSEG (T)
(TOLUD–STOLEN–TSEG) to TOLUD–
STOLEN
(TOLUD–STOLEN–TSEG) to TOLUD–
STOLEN