Intel i7-2600 CM8062300834302S User Manual

Datasheet, Volume 2

79

This 32 bit register defines the Top of Low Usable DRAM. TSEG, GTT Graphics memory 
and Graphics Stolen Memory are within the DRAM space defined. From the top, the 
Host optionally claims 1 to 64 MBs of DRAM for internal graphics if enabled, 1 or 2 MB 
of DRAM for GTT Graphics Stolen Memory (if enabled) and 1, 2, or 8 MB of DRAM for 
TSEG if enabled.

Programming Example:

• C1DRB3 is set to 4 GB.
• TSEG is enabled and TSEG size is set to 1 MB.
• Internal Graphics is enabled, and Graphics Mode Select is set to 32 MB.
• GTT Graphics Stolen Memory Size set to 2 MB.
• BIOS knows the OS requires 1G of PCI space.
• BIOS also knows the range from 0_FEC0_0000h to 0_FFFF_FFFFh is not usable by 

the system. This 20 MB range at the very top of addressable memory space is lost 
to APIC and Intel TXT.

• According to the above equation, TOLUD is originally calculated to: 4 GB = 

1_0000_0000h.

• The system memory requirements are: 4 GB (max addressable space) – 1 GB (pci 

space) = 0_C000_0000h. Since 0_C000_0000h (PCI and other system 
requirements) is less than 1_0000_0000h, TOLUD should be programmed to C00h.

These bits are Intel TXT lockable.

31:20

RW-L

001h

Uncore

Top of Low Usable DRAM (TOLUD)
This register contains bits 31:20 of an address one byte above the 

maximum DRAM memory below 4 GB that is usable by the 

operating system. Address bits 31:20 programmed to 01h implies 

a minimum memory size of 1 MB. Configuration software must set 

this value to the smaller of the following 2 choices: maximum 

amount memory in the system minus Intel ME stolen memory plus 

one byte or the minimum address allocated for PCI memory. 

Address bits 19:0 are assumed to be 0_0000h for the purposes of 

address comparison. The Host interface positively decodes an 

address towards DRAM if the incoming address is less than the 

value programmed in this register.
The Top of Low Usable DRAM is the lowest address above both 

Graphics Stolen memory and TSEG. BIOS determines the base of 

Graphics Stolen Memory by subtracting the Graphics Stolen 

Memory Size from TOLUD and further decrements by TSEG size to 

determine base of TSEG. All the Bits in this register are locked in 

Intel TXT mode.
This register must be 1MB aligned when reclaim is enabled.

19:1

RO

0h

0

RW-KL

0b

Uncore

Lock (LOCK)
This bit will lock all writeable settings in this register, including 

itself.