Intel i7-2600 CM8062300834302S User Manual

86

Datasheet, Volume 2

15:11

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INTA Assertion Disable (INTAAD)
0 = This device is permitted to generate INTA interrupt messages

.

1 = This device is prevented from generating interrupt messages. 

Any INTA emulation interrupts already asserted must be de-

asserted when this bit is set. 

Only affects interrupts generated by the device (PCI INTA from a 

PME or Hot Plug event) controlled by this command register. It 

does not affect upstream MSIs, upstream PCI INTA–INTD assert 

and deassert messages.

9

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Fast Back-to-Back Enable (FB2B)
Not Applicable or Implemented. Hardwired to 0. 

8

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SERR# Message Enable (SERRE)
This bit controls the root port SERR# messaging. The processor 

communicates the SERR# condition by sending an SERR message 

to the PCH. This bit, when set, enables reporting of non-fatal and 

fatal errors detected by the device to the Root Complex. Note that 

errors are reported if enabled either through this bit or through the 

PCI-Express specific bits in the Device Control Register.
In addition, for Type 1 configuration space header devices, this bit, 

when set, enables transmission by the primary interface of 

ERR_NONFATAL and ERR_FATAL error messages forwarded from 

the secondary interface. This bit does not affect the transmission of 

forwarded ERR_COR messages.
0 = The SERR message is generated by the root port only under 

conditions enabled individually through the Device Control 

Register.

1 = The root port is enabled to generate SERR messages that will 

be sent to the PCH for specific root port error conditions 

generated/detected or received on the secondary side of the 

virtual PCI to PCI bridge. The status of SERRs generated is 

reported in the PCISTS register.

7

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6

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Parity Error Response Enable (PERRE)
This bit controls whether or not the Master Data Parity Error bit in 

the PCI Status register can bet set.
0 = Master Data Parity Error bit in PCI Status register can NOT be 

set.

1 = Master Data Parity Error bit in PCI Status register CAN be set.

5

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VGA Palette Snoop (VGAPS)
Not Applicable or Implemented. Hardwired to 0. 

4

RO

0b

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Memory Write and Invalidate Enable (MWIE)
Not Applicable or Implemented. Hardwired to 0. 

3

RO

0b

Uncore

Special Cycle Enable (SCE)
Not Applicable or Implemented. Hardwired to 0.