AMD Sempron 3300 box S754 SDA3300BOX User Manual
Product codes
SDA3300BOX
12
Power Management
Chapter 4
AMD Sempron™ Processor Model 10 Data Sheet
31993A-1 September 2004
AMD Preliminary Information
In C2, probes are allowed, as shown in Figure 3 on page 9
The Stop Grant state is also entered for the S1, Powered On
Suspend, system sleep state based on a write to the SLP_TYP
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 Sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Suspend, system sleep state based on a write to the SLP_TYP
and SLP_EN fields in the ACPI-defined Power Management 1
control register in the Southbridge. During the S1 Sleep state,
system software ensures no bus master or probe activity occurs.
The Southbridge deasserts STPCLK# and brings the processor
out of the S1 Stop Grant state when any enabled resume event
occurs.
Probe State
The Probe state is entered when the Northbridge connects the
AMD Athlon system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Athlon system bus again.
AMD Athlon system bus to probe the processor (for example, to
snoop the processor caches) when the processor is in the Halt or
Stop Grant state. When in the Probe state, the processor
responds to a probe cycle in the same manner as when it is in
the Working state. When the probe has been serviced, the
processor returns to the same state as when it entered the
Probe state (Halt or Stop Grant state). When probe activity is
completed the processor only returns to a low-power state after
the Northbridge disconnects the AMD Athlon system bus again.
4.2
Connect and Disconnect Protocol
Significant power savings of the processor only occur if the
proc e ss o r is di s co nn ec t e d f ro m t h e sy s t e m b u s by t h e
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
proc e ss o r is di s co nn ec t e d f ro m t h e sy s t e m b u s by t h e
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
Connect Protocol
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an