AMD CPU AMD Sempron SocA 2800+ 256Kb BOX SDA2800BOX User Manual

31993A-1 September 2004

The chipset samples the FID[3:0] signals in a chipset-specific 
manner from the processor and uses this information to 
determine the correct serial initialization packet (SIP). The 
chipset then sends the SIP information to the processor for 
configuration of the AMD Athlon system bus for the clock 
multiplier that determines the processor frequency indicated 
by the FID[3:0] code. The SIP is sent to the processor using the 
SIP protocol. This protocol uses the PROCRDY, CONNECT, and 
CLKFWDRST signals, that are synchronous to SYSCLK.

For more information about FID[3:0], see “FID[3:0] Pins” on 
page 70.

Serial Initialization Packet (SIP) Protocol.  Refer to AMD Athlon™ and 
AMD Duron™ System Bus Specification, order# 21902 for details 
of the SIP protocol.

RESET# cannot be asserted to the processor without also being 
asserted to the Northbridge. RESET# to the Northbridge is the 
same as PCI RESET#. The minimum assertion for PCI RESET# 
is one millisecond. Southbridges enforce a minimum assertion 
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0 
milliseconds.