AMD Sempron 3300 box S754 SDA3300BABOX User Manual
Product codes
SDA3300BABOX
18
Power Management
Chapter 4
AMD Sempron™ Processor Model 10 Data Sheet
31993A-1 September 2004
AMD Preliminary Information
4.3
Clock Control
The processor implements a Clock Control (CLK_Ctl) MSR
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
(address C001_001Bh) that determines the internal clock
divisor when the AMD Athlon system bus is disconnected.
Refer to the AMD Athlon™ and AMD Duron™ Processors BIOS,
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.
Software, and Debug Developers Guide, order# 21656, for more
details on the CLK_Ctl register.