Intel i5-2510E FF8062700853304 User Manual

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Datasheet

The processor supports the following Intel VT-d features:

• Integrated graphics and memory controller comply with Intel® VT-d 1.0a 

Specification. 

• Three Intel VT-d DMA remap engines.

— iGFX DMA remap engine
— DMI (non-high definition audio)/PEG
— DMI high definition audio

• 36-bit guest physical address and host physical address widths.
• Support for 4-K page sizes only.
• Support for register-based fault recording only (for single entry only) and support 

for MSI interrupts for faults,

— Support for fault collapsing based on Requester ID, OS-visible ME PCI devices

• Support for both leaf and non-leaf caching.
• Support for boot protection of default page table.
• Support for non-caching of invalid page table entries.
• Support for hardware based flushing of translated but pending writes and pending 

reads on IOTLB invalidation.

• Support for page-selective IOTLB invalidation.
• MSI cycles (MemWr to address FEEx_xxxxh) not translated.
• Translation faults result in cycle forwarding to VBIOS region (byte enables masked 

for writes).

— Returned data may be bogus for internal agents, PEG/DMI interfaces return 

unsupported request status.

The following features are not supported by the processor with Intel VT-d:

• No support for PCI-SIG endpoint caching (ATS).
• No support for interrupt remapping.
• No support for queue-based invalidation interface.
• No support for Intel VT-d read prefetching/snarfing, i.e., translations within a 

cacheline are not stored in an internal buffer for reuse for subsequent translations.

• No support for advance fault reporting.
• No support for super pages.
• No support for 1 or 2 level page walks for isoch remap engine and 1, 2, or 3 level 

walks for non-isoch remap engine.

• No support for Intel VT-d translation bypass address range (such usage models 

need to be resolved with VMM help in setting up the page tables correctly).