Intel i5-2510E FF8062700853304 User Manual

46

Datasheet

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to 

the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its 

L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while 

maintaining its architectural state. All core clocks are stopped at this point. Because the 

core’s caches are flushed, the processor does not wake any core that is in the C3 state 

when either a snoop is detected or when another core accesses cacheable memory.

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an 

MWAIT(C6) instruction. Before entering core C6, the core will save its architectural 

state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero 

volts. During exit, the core is powered on and its architectural state is restored.

In general, deeper C-states such as C6 have long latencies and have higher energy 

entry/exit costs. The resulting performance and energy penalties become significant 

when the entry/exit frequency of a deeper C-state is high. Therefore, incorrect or 

inefficient usage of deeper C-states have a negative impact on battery life. In order to 

increase residency and improve battery life in deeper C-states, the processor supports 

C-state auto-demotion.

There are two C-State auto-demotion options:

• C6  to  C3
• C6/C3 To C1

The decision to demote a core from C6 to C3 or C3/C6 to C1 is based on each core’s 

immediate residency history. Upon each core C6 request, the core C-state is demoted 

to C3 or C1 until a sufficient amount of residency has been established. At that point, a 

core is allowed to go into C3/C6. Each option can be run concurrently or individually.

This feature is disabled by default. BIOS must enable it in the 

PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by 

this register. 

The processor supports C0, C1/C1E, C3, and C6 package idle power states. The 

following is a summary of the general rules for package C-state entry. These apply to 

all package C-states unless specified otherwise:

• A package C-state request is determined by the lowest numerical core C-state 

amongst all cores.

• A package C-state is automatically resolved by the processor depending on the 

core idle power states and the status of the platform components.

— Each core can be at a lower idle power state than the package if the platform 

does not grant the processor permission to enter a requested package C-state.

— The platform may allow additional power savings to be realized in the 

processor. 

• For package C-states, the processor is not required to enter C0 before entering any 

other C-state.