Intel i5-2520M FF8062700840017 User Manual

Datasheet

71

SB_DQS[7:0]

Data Strobes: SB_DQS[7:0] and its 
complement signal group make up a 
differential strobe pair. The data is captured 
at the crossing point of SB_DQS[7:0] and its 
SB_DQS#[7:0] during read and write 
transactions.

I/O

DDR3 

SB_DQS#[7:0]

Data Strobe Complements: These are the 
complementary strobe signals.

I/O

DDR3 

SB_DQ[63:0]

Data Bus: Channel B data signal interface to 
the SDRAM data bus.

I/O

DDR3 

SB_MA[15:0]

Memory Address: These signals are used to 
provide the multiplexed row and column 
address to the SDRAM.

O

DDR3

SB_CK[1:0]

SDRAM Differential Clock: Channel B 
SDRAM Differential clock signal pair. The 
crossing of the positive edge of SB_CK and 
the negative edge of its complement 
SB_CK# are used to sample the command 
and control signals on the SDRAM.

O

DDR3

SB_CK#[1:0]

SDRAM Inverted Differential Clock: 
Channel B SDRAM Differential clock signal-
pair complement.

O

DDR3

SB_CKE[1:0]

Clock Enable: (1 per rank) Used to:
- Initialize the SDRAMs during power-up.
- Power-down SDRAM ranks.
- Place all SDRAM ranks into and out of self-
refresh during STR.

O

DDR3

SB_CS#[1:0]

Chip Select: (1 per rank) Used to select 
particular SDRAM components during the 
active state. There is one Chip Select for 
each SDRAM rank.

O

DDR3

SB_ODT[1:0]

On Die Termination: Active Termination 
Control.

O

DDR3

SA_DIMM_VREFDQ
SB_DIMM_VREFDQ

O

A

SM_RCOMP[2:0]

I

A