Intel i5-2520M FF8062700840017 User Manual

Datasheet

83

The processor has V

CC

, V

TT

, V

DDQ, 

V

CCPLL, 

V

AXG

 and V

SS 

(ground) inputs for on-chip 

power distribution. All power pins must be connected to their respective processor 

power planes, while all V

SS

 pins must be connected to the system ground plane. Use of 

multiple power and ground planes is recommended to reduce I*R drop. The V

CC

 pins 

must be supplied with the voltage determined by the processor Voltage IDentification 

(VID) signals.Likewise, the V

AXG

 pins must also be supplied with the voltage 

determined by the GFX_VID signals. 

 specifies the voltage level for the various 

VIDs. The voltage levels are the same for both the processor VIDs and GFX_VIDs.

Due to its large number of transistors and high internal clock speeds, the processor is 

capable of generating large current swings between low- and full-power states. To keep 

voltages within specification, output decoupling must be properly designed.

Design the board to ensure that the voltage provided to the processor remains within 

the specifications listed in 

. Failure to do so can result in timing violations or 

reduced lifetime of the processor. 

The voltage regulator solution must:

• provide sufficient decoupling to compensate for large current swings generated 

during different power mode transitions.

• provide low parasitic resistance from the regulator to the socket.
• meet voltage and current specifications as defined in 

The processor utilizes a differential clock to generate the processor core(s) operating 

frequency, memory controller frequency, and other internal clocks. The processor core 

frequency is determined by multiplying the processor core ratio by 133 MHz. Clock 

multiplying within the processor is provided by an internal phase locked loop (PLL), 

which requires a constant frequency input, with exceptions for Spread Spectrum 

Clocking (SSC). 

The processor’s maximum core frequency is configured during power-on reset by using 

its manufacturing default value. This value is the highest core multiplier at which the 

processor can operate. 

An on-die PLL filter solution is implemented on the processor. Refer to 

 for DC 

specifications.