Intel E5-2440 BX80621E52440 User Manual

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

149

Datasheet Volume One

PROCHOT_N

PROCHOT_N will go active when the processor temperature monitoring sensor detects 

that the processor has reached its maximum safe operating temperature. This indicates 

that the processor Thermal Control Circuit has been activated, if enabled. This signal can 

also be driven to the processor to activate the Thermal Control Circuit. This signal is 

sampled after PWRGOOD assertion.
If PROCHOT_N is asserted at the deassertion of RESET_N, the processor will tristate its 

outputs.

PWRGOOD

Power Good is a processor input. The processor requires this signal to be a clean 

indication that BCLK, VTTA/VTTD, VSA, VCCPLL, and VCCD_01 and VCCD_23 supplies are 

stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current), 

without glitches, from the time that the power supplies are turned on until they come 

within specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be stable 

before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from inactive to 

active when all supplies except VCC are stable. VCC has a VBOOT of zero volts and is not 

included in PWRGOOD indication in this phase. However, for the active to inactive 

transition, if any CPU power supply (VCC, VTTA/VTTD, VSA, VCCD, or VCCPLL) is about to 

fail or is out of regulation, the PWRGOOD is to be negated.
The signal must be supplied to the processor; it is used to protect internal circuits against 

voltage sequencing issues. It should be driven high throughout boundary scan operation.

VCC has a Vboot setting of 0.0V and is not included in the PWRGOOD indication 

and VSA has a Vboot setting of 0.9V. Refer to the VR12/IMVP7 Pulse Width 

.

RESET_N

Asserting the RESET_N signal resets the processor to a known state and invalidates its 

internal caches without writing back any of their contents. Note some PLL, Intel 

QuickPath Interconnect and error states are not effected by reset and only PWRGOOD 

forces them to a known state.

RSVD

RESERVED. All signals that are RSVD must be left unconnected on the board. Refer to 

 for details. 

SAFE_MODE_BOOT

Safe mode boot Strap. SAFE_MODE_BOOT allows the processor to wake up safely by 

disabling all clock gating, this allows BIOS to load registers or patches if required. This 

signal is sampled after PWRGOOD assertion. The signal is pulled down on the die, refer to 

 for details. 

SOCKET_ID[1:0]

Socket ID Strap. Socket identification configuration straps for establishing the PECI 

address, Intel QPI Node ID, and other settings. This signal is used in combination with 

FRMAGENT to determine whether the socket is a legacy socket, bootable firmware agent 

is present, and DMI links are used in PCIe* mode (instead of DMI2 mode). Each 

processor socket consumes one Node ID, and there are 128 Home Agent tracker entries. 

This signal is pulled down on the die, refer to 

 for details.

TEST[4:0]

Test[4:0] must be individually connected to an appropriate power source or ground 

through a resistor for proper processor operation. Refer to the appropriate Platform 

Design Guide (PDG) for additional implementation details.

THERMTRIP_N

Assertion of THERMTRIP_N (Thermal Trip) indicates one of two possible critical over-

temperature conditions: One, the processor junction temperature has reached a level 

beyond which permanent silicon damage may occur and Two, the system memory 

interface has exceeded a critical temperature limit set by BIOS. Measurement of the 

processor junction temperature is accomplished through multiple internal thermal 

sensors that are monitored by the Digital Thermal Sensor (DTS). Simultaneously, the 

Power Control Unit (PCU) monitors external memory temperatures via the dedicated 

SMBus interface to the DIMMs. If any of the DIMMs exceed the BIOS defined limits, the 

PCU will signal THERMTRIP_N to prevent damage to the DIMMs. Once activated, the 

processor will stop all execution and shut down all PLLs. To further protect the processor, 

its core voltage (VCC), VTTA, VTTD, VSA, VCCPLL, VCCD supplies must be removed 

following the assertion of THERMTRIP_N. Once activated, THERMTRIP_N remains latched 

until RESET_N is asserted. While the assertion of the RESET_N signal may de-assert 

THERMTRIP_N, if the processor's junction temperature remains at or above the trip level, 

THERMTRIP_N will again be asserted after RESET_N is de-asserted. This signal can also 

be asserted if the system memory interface has exceeded a critical temperature limit set 

by BIOS. This signal is sampled after PWRGOOD assertion.