Intel T1350 LF80538GE0362M User Manual

52

Datasheet

DINV[3:0]#

Input/

Output

DINV[3:0]# (Data Bus Inversion) are source synchronous and 
indicate the polarity of the D[63:0]# signals. The DINV[3:0]# 
signals are activated when the data on the data bus is inverted. The 
bus agent will invert the data bus signals if more than half the bits, 
within the covered group, would change level in the next cycle.

DPRSTP#

Input

 DPRSTP# when asserted on the platform causes the processor to 
transition from the Deep Sleep State to the Deeper Sleep state. In 
order to return to the Deep Sleep State, DPRSTP# must be 
deasserted. DPRSTP# is driven by the Intel® ICH7M chipset.

DPSLP#

Input

DPSLP# when asserted on the platform causes the processor to 
transition from the Sleep State to the Deep Sleep state. In order to 
return to the Sleep State, DPSLP# must be deasserted. DPSLP# is 
driven by the ICH7M chipset.

DPWR#

Input

DPWR# is a control signal from the Mobile Intel

 

945 Express 

Chipset family used to reduce power on the processor data bus 
input buffers.

DRDY#

Input/

Output

DRDY# (Data Ready) is asserted by the data driver on each data 
transfer, indicating valid data on the data bus. In a multi-common 
clock data transfer, DRDY# may be deasserted to insert idle clocks. 
This signal must connect the appropriate pins of both FSB agents.

DSTBN[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

DSTBP[3:0]#

Input/

Output

Data strobe used to latch in D[63:0]#.

DINV[3]#

D[63:48]#

DINV[2]#

D[47:32]#

DINV[1]#

D[31:16]#

DINV[0]#

D[15:0]#

D[15:0]#, DINV[0]# 

DSTBN[0]#

D[31:16]#, DINV[1]#  DSTBN[1]#

D[47:32]#, DINV[2]#  DSTBN[2]#

D[63:48]#, DINV[3]#  DSTBN[3]#

D[15:0]#, DINV[0]# 

DSTBP[0]#

D[31:16]#, DINV[1]#  DSTBP[1]#

D[47:32]#, DINV[2]#  DSTBP[2]#

D[63:48]#, DINV[3]#  DSTBP[3]#