Intel III 600 MHz 80526PZ600256 User Manual
Product codes
80526PZ600256
42
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
Figure 10. BCLK, PICCLK, and TCK Generic Clock Waveform
Figure 11. System Bus Valid Delay Timings
V3
V1
V2
T
p
T
l
T
h
T
r
T
f
Vringback
(rise)
Vringback
(fall)
T
r
= T5, T25, T34, (R ise Tim e)
T
f
= T6, T26, T35, (Fall Tim e)
T
h
= T3, T23, T32, (H igh Tim e)
T
l
= T4, T24, T33, (Low Tim e)
T
p
= T1, T22, T31 (BC LK, TC K, PIC C LK Period)
V1 =
B C LK is referenced to 0.30V (D ifferential M ode), 0.50V (Single-Ended M ode)
TC K is referenced to Vref - 200 m V, PIC C LK is referenced to 0.4V.
V2 =
B C LK is refernced to 0.9V (D ifferental M ode), 2.0V (Single-E nded M ode)
TC K is referenced to Vref + 200 m V, PIC C LK is refernced to 1.6V
V3 =
B C LK and BLC K # crossing point of the rising edge of BLC K and the falling edge of BC LK# (D ifferential M ode),
BC LK i refereced to 1.25V (Single-Ended M ode), PIC C LK is reference to 1.0V, TC K is referenced to Vcm osref
0V
Vih diff
Vil diff
BCLK
Signal
Valid
Tx
V
Tx
Tpw
Tx = T7, T11, T29a, T29b (Valid Delay)
Tpw = T14, T15 (Pulse Width)
V = Vref for AGTL signal group; Vcmosref for CMOS, APIC and TAP signal groups
BCLK#
Valid
NOTE: Single-Ended clock uses BCLK only,
Differential clock uses BCLK and BCLK#
Differential clock uses BCLK and BCLK#