Intel III 600 MHz 80526PZ600256 User Manual
Product codes
80526PZ600256
Datasheet
55
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.4.2
Ringback Specification
Ringback refers to the amount of reflection seen after a signal has switched. The ringback
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See
specification is the voltage that the signal rings back to after achieving its maximum absolute
value. See
Figure 20
for an illustration of ringback. Excessive ringback can cause false signal
detection or extend the propagation delay. The ringback specification applies to the input pin of
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ (non-AGTL) signals.
each receiving agent. Violations of the signal ringback specification are not allowed under any
circumstances for non-AGTL+ (non-AGTL) signals.
Ringback can be simulated with or without the input protection diodes that can be added to the
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See
input buffer model. However, signals that reach the clamping voltage should be evaluated further.
See
Table
for the signal ringback specifications for non-AGTL+ signals for simulations at the
processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Non-AGTL+ signals except PWRGOOD.
2. Non-AGTL+ signals except PWRGOOD.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processor frequencies.
2. Non-AGTL signals except PWRGOOD.
3. For Coppermine-T with differential clocking, this signal is 1.8 V tolerant.
2. Non-AGTL signals except PWRGOOD.
3. For Coppermine-T with differential clocking, this signal is 1.8 V tolerant.
3.4.3
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10% of the total signal swing (V
before its next transition. The amount allowed is 10% of the total signal swing (V
HI
–
V
LO
) above
and below its final value. A signal should be within the settling limits of its final value, when either
in its high state or low state, before it transitions again.
in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
Table 28. Signal Ringback Specifications for Non-AGTL+ Signal Simulations at the Processor
Pins
1
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
2
0
→
1
V
CMOS_REF
+ 0.200
V
20
Non-AGTL+ Signals
2
1
→
0
V
CMOS_REF
- 0.200
V
20
PWRGOOD
0
→
1
2.00
V
20
Table 29. Signal Ringback Specifications for Non-AGTL Signal Simulations at the Processor
Pins
1
Input Signal Group
Transition
Maximum Ringback
(with Input Diodes Present)
Unit
Figure
Non-AGTL+ Signals
2
0
→
1
V
CMOS_REF
+ 0.200
V
20
Non-AGTL+ Signals
2
1
→
0
V
CMOS_REF
- 0.300
V
20
PWRGOOD
0
→
1
2.00
3
V
20