Intel III 600 MHz 80526PY600256 User Manual

Product codes

80526PY600256

Datasheet

Pentium

III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz

Note:

References to BCLK throughout this document will also imply to its complement signal, BCLK#,
in differential implementations and when noted otherwise.

For a differential clock input, all AGTL system bus timing parameters are specified with respect to
the crossing point of the rising edge of the BCLK input and the falling edge of the BCLK# input.
See the P6 Family of Processors Hardware Developer's Manual for further details.

Note:

For differential clocking, the reference voltage of the BCLK in the P6 Family of Processors
Hardware Developer's Manual is re-defined as the crossing point of the BCLK and the BCLK#
inputs.

2.5.1

Mixing Processors of Different Frequencies

In two-way MP (multi-processor) systems, mixing processors of different internal clock
frequencies is not supported and has not been validated. Pentium

III

processors do not support a

variable multiplier ratio; therefore, adjusting the ratio setting to a common clock frequency is not
valid. However, mixing processors of the same frequency but of different steppings is supported.
Details on support for mixed steppings is provided in the Pentium

III

Processor Specification

Update.

Note:

Not all Pentium

III

processors for the PGA370 socket are validated for use in dual processor (DP)

systems. Refer to the Pentium

III

Processor Specification Update to determine which processors

are DP capable.

2.6

Voltage Identification

There are four voltage identification pins on the PGA370 socket. These pins can be used to support
automatic selection of V

CCCORE

voltages. These pins are not signals, but are either an open circuit

or a short circuit to V

on the processor. The combination of opens and shorts defines the voltage

required by the processor core. The VID pins are needed to cleanly support voltage specification
variations on current and future processors. VID[3:0] are defined in

Table 2

. A ‘1’ in this table

refers to an open pin and a ‘0’ refers to a short to ground. The voltage regulator or VRM must
supply the voltage that is requested or disable itself.

To ensure a system is ready for current and future processors, the range of values in bold in

Table 2

should be supported. A smaller range will risk the ability of the system to migrate to a higher
performance processor and/or maintain compatibility with current processors.

Figure 6. Differential Clocking Example

BCLK

BCLK#

Clock
Driver

Processor or
Chipset