Intel III 600 MHz 80526PY600256 User Manual
Product codes
80526PY600256
46
Datasheet
Pentium
®
III Processor for the PGA370 Socket at 500 MHz to 1.13 GHz
3.0
Signal Quality Specifications
Signals driven on the processor system bus should meet signal quality specifications to ensure that
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in
the components read data properly and to ensure that incoming signals do not affect the long term
reliability of the component. Specifications are provided for simulation at the processor pins.
Meeting the specifications at the processor pins in
Table 21
,
Table
,
Table 23
,
Table
, and
Table
ensures that signal quality effects will not adversely affect processor operation.
3.1
BCLK/BCLK# and PICCLK Signal Quality Specifications
and Measurement Guidelines
and Measurement Guidelines
Table 21
describes the signal quality specifications at the processor pins for the processor system
bus clock (BCLK) and APIC clock (PICCLK) signals.
Figure 16
describes the signal quality
waveform for the system bus clock at the processor pins.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all Pentium III processors frequencies.
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
2. The rising and falling edge ringback voltage specified is the minimum (rising) or maximum (falling) absolute
voltage the BCLK/PICCLK signal can dip back to after passing the V
IH
(rising) or V
IL
(falling) voltage limits.
This specification is an absolute value.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Pentium III processors that support the AGTL
specification. Refer to the Intel
®
Pentium
®
III Processor Specification Update for a complete listing on the
processors that support the AGTL specification.
Table 21. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins
1
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: BCLK V
IL
0.500
V
16
V1: PICCLK V
IL
0.700
V
16
V2: BCLK V
IH
2.000
V
16
V2 PICCLK V
IH
2.000
V
16
V3: V
IN
Absolute Voltage Range
–0.58
3.18
V
16
V4: BCLK Rising Edge Ringback
2.000
V
16
2
V4: PICCLK Rising Edge Ringback
2.000
V
16
2
V5: BCLK Falling Edge Ringback
0.500
V
16
2
V5: PICCLK Falling Edge Ringback
0.700
V
16
2
Table 22. BCLK/PICCLK Signal Quality Specifications for Simulation at the Processor Pins in
a Differential Clock Platform for AGTL
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
V1: PICCLK V
IL
0.40
V
16
V2 PICCLK V
IH
1.60
V
16
V3: PICCLK Absolute Voltage
Range
Range
-0.4
2.4
V
16
V4: PICCLK Rising Edge Ringback
1.60
V
16
2
V5: PICCLK Falling Edge Ringback
0.40
V
16
2