Intel III Xeon 800 MHz 80526KZ800256 User Manual
Product codes
80526KZ800256
ELECTRICAL SPECIFICATIONS
13
A20M#
IGNNE#
LINT1/NMI
LINT0/INTR
Processors
1K Ω
2.5 V
Set Ratio:
CRESET#
2
Mux
2.5 V
1-4
000809
Figure 2. Logical1 Schematic for Clock Ratio Pin Sharing
NOTES:
1.
1.
Signal Integrity issues may require this circuit to be modified
2.
Current Intel® 840 chipsets do not implement the CRESET# signal.
3.4.2 MIXING PROCESSORS OF DIFFERENT FREQUENCIES
Mixing components of different internal clock frequencies is not supported and has not been validated by Intel. Operating
system support for multi-processing with mixed frequency components should also be considered.
Also, Intel® does not support or validate operation of processors with different cache sizes. Intel® only supports and
validates multi-processor configurations where all processors operate with the same system bus and core frequencies
and have the same L1 and L2 cache sizes. Since the Pentium® III Xeon™ processor at 900 MHz with 2MB of L2 cache
will operate only with a 9:1 core/bus ratio, this processor should only be used in systems containing identical processors.
Intel® does not support or validate the mixing of Pentium® III Xeon™ processors at 500 MHz and 550 MHz, Pentium® III
Xeon™ processors at 700 MHz and 900 MHz, Pentium® III Xeon™ processors at 600 MHz to 1 GHz with 256KB L2
cache, and Pentium® II Xeon™ processors on the same system bus, regardless of frequency or L2 cache sizes.
system support for multi-processing with mixed frequency components should also be considered.
Also, Intel® does not support or validate operation of processors with different cache sizes. Intel® only supports and
validates multi-processor configurations where all processors operate with the same system bus and core frequencies
and have the same L1 and L2 cache sizes. Since the Pentium® III Xeon™ processor at 900 MHz with 2MB of L2 cache
will operate only with a 9:1 core/bus ratio, this processor should only be used in systems containing identical processors.
Intel® does not support or validate the mixing of Pentium® III Xeon™ processors at 500 MHz and 550 MHz, Pentium® III
Xeon™ processors at 700 MHz and 900 MHz, Pentium® III Xeon™ processors at 600 MHz to 1 GHz with 256KB L2
cache, and Pentium® II Xeon™ processors on the same system bus, regardless of frequency or L2 cache sizes.
3.5 Voltage Identification
The Pentium® III Xeon™ processor at 700 MHz and 900 MHz FMB guidelines enable compatibility with systems originally
designed for previous members of the Pentium® II Xeon™ and Pentium® III Xeon™ processor family. To provide power
delivery flexibility, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz is available in two different input voltage
versions; one version operates at 2.8 Volts and the other at 5 Volts or 12 Volts. As in previous versions of Pentium® II
Xeon™ and Pentium® III Xeon™ processors, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz contains five
voltage identification (VID) pins, which are used by the processor for OCVR voltage selection in combination with pin A3,
which incorporates added functionality for power delivery schemes.
The Pentium® III Xeon™ processor at 700 MHz and 900 MHz incorporates a new pin (A3, HV_EN#) as a method to
identify its ability to be powered by a 5V or 12V power supply. The HV_EN# signal is used as a way of differentiating a
5V/12V version processor cartridge from a 2.8V version. HV_EN# is tied to Vss (ground) on the 5V/12V version, and is
high impedance (floating) on the 2.8V version. This is a reserved (no connect) pin on previous versions of the Pentium®
III Xeon™ processor.
Since the L2 cache is integrated in the core, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not
require a VID code to specify cache voltage. Pentium® III Xeon™ processor at 700 MHz and 900 MHz FMB designs
could be implemented to provide the additional five voltage identification pins for L2 cache voltage selection if Pentium® II
Xeon™ processor and previous versions of Pentium® III Xeon™ processor compatibility are desired. These pins may be
used to support automatic selection of both power supply voltages as required by a specific cartridge.
designed for previous members of the Pentium® II Xeon™ and Pentium® III Xeon™ processor family. To provide power
delivery flexibility, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz is available in two different input voltage
versions; one version operates at 2.8 Volts and the other at 5 Volts or 12 Volts. As in previous versions of Pentium® II
Xeon™ and Pentium® III Xeon™ processors, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz contains five
voltage identification (VID) pins, which are used by the processor for OCVR voltage selection in combination with pin A3,
which incorporates added functionality for power delivery schemes.
The Pentium® III Xeon™ processor at 700 MHz and 900 MHz incorporates a new pin (A3, HV_EN#) as a method to
identify its ability to be powered by a 5V or 12V power supply. The HV_EN# signal is used as a way of differentiating a
5V/12V version processor cartridge from a 2.8V version. HV_EN# is tied to Vss (ground) on the 5V/12V version, and is
high impedance (floating) on the 2.8V version. This is a reserved (no connect) pin on previous versions of the Pentium®
III Xeon™ processor.
Since the L2 cache is integrated in the core, the Pentium® III Xeon™ processor at 700 MHz and 900 MHz does not
require a VID code to specify cache voltage. Pentium® III Xeon™ processor at 700 MHz and 900 MHz FMB designs
could be implemented to provide the additional five voltage identification pins for L2 cache voltage selection if Pentium® II
Xeon™ processor and previous versions of Pentium® III Xeon™ processor compatibility are desired. These pins may be
used to support automatic selection of both power supply voltages as required by a specific cartridge.